Session 3: Schematic & Simulation¶

Summary¶¶

Schematic capture is the first step in circuit design SPICE simulates circuit behavior with detailed models Analysis types: DC, AC, Transient, Operating Point PDK libraries provide calibrated device models Corner simulation ensures robustness across process variation

Homework¶

Reuse and.sp netlist, which has a 2-input AND gate to make a 2-input NAND gate (e.g., remove the output inverter) and change the models to refer to the PDK models Simulate it in SPICE, verify truth table (it will look something like the right table), and measure propagation delays (low-to-high and high-to-low) Write an initial analog block that you can use in your chip project (e.g., an adder, counter, etc.) Here’s a good starting point: https://analoghub.ie/category/verilogModels/article/counter

Assignment 1¶

Reuse and.sp netlist, which has a 2-input AND gate to make a 2-input NAND gate (e.g., remove the output inverter) and change the models to refer to the PDK models

First, I checked AND netlist again.

This is a netlist of AND gate.

* AND gate ngspice example

* NGSPICE transistor models
.model mosn NMOS level=49 version=3.3.0 tox=10n nch=1e17 nsub=5e16 
.model mosp PMOS level=49 version=3.3.0 tox=10n nch=1e17 nsub=5e16

* 1 V power supply
vsup VDD 0 1 


* AND pull-up network -- two pmos in parallel
Mp1 nOUT A VDD VDD mosp L=0.35u W=2u 
Mp2 nOUT B VDD VDD mosp L=0.35u W=2u


* Pull-down network -- two nmos in series
Mn1 nOUT A npd 0 mosn L=0.35u W=2u 
Mn2 npd B 0 0 mosn L=0.35u W=2u

* Inverter, or a logical NOT
Mp3 AND nOUT VDD VDD mosp L=0.35u W=2u
Mn3 AND nOUT 0 0 mosn L=0.35u W=2u

* Input voltage source, ramps up to VDD then back down
vin1 A 0 PWL(0 0 2mS 0 2.001mS 1V 3mS 1V 3.001mS 0) 
vin2 B 0 PWL(0 0 1mS 0 1.001mS 1V 2.5mS 1V 2.5001mS 0) 

.control 
* transient simulation using vin sweep
  tran 100n 4m 

* plot vout against vin 
  plot v(A) 
  plot v(B) 
  plot v(AND)
.endc

I tried to think about schematic of NAND gate.

It is inverse of AND. So I just removed the NOT gate from the end of AND gate.

Then I tried to write netlist. I just removed the NOT gate part and changed the symbol “nOUT” into “OUT”.

``` * NAND gate ngspice TAKE designed

NGSPICE transistor models .lib “/foss/pdks/sky130A/libs.tech/ngspice/sky130.lib.spice” tt
1.8 V power supply vsup VDD 0 1.8
NAND pull-up network – two pmos in parallel Mp1 NAND A VDD VDD sky130_fd_pr__pfet_01v8 L=0.35u W=2u Mp2 NAND B VDD VDD sky130_fd_pr__pfet_01v8 L=0.35u W=2u
Pull-down network – two nmos in series Mn1 NAND A npd 0 sky130_fd_pr__nfet_01v8 L=0.35u W=2u Mn2 npd B 0 0 sky130_fd_pr__nfet_01v8 L=0.35u W=2u
Input voltage source, ramps up to VDD then back down vin1 A 0 PWL(0 0 2mS 0 2.001mS 1V 3mS 1.8V 3.001mS 0) vin2 B 0 PWL(0 0 1mS 0 1.001mS 1V 2.5mS 1.8V 2.5001mS 0)

.control * transient simulation using vin sweep tran 100n 4m

plot vout against vin plot v(A) plot v(B) plot v(NAND) .endc

```

run simulation¶

```

Run ngspice in batch mode¶

ngspice -b nand.sp

Or run interactively¶

ngspice nand.sp ```

Change the M to X(use sub circuit)
Change .lin into .include

I had errors and couldn’t run the script. I couldn’t succeed by my self. Then I checked other participants’s page. I tried to copy Phillippe’s netlist.

I could run his netlist in my environment. After that, I change property of input.

* NAND gate ngspice with PDK

* Include the Sky130 device models
.lib "/foss/pdks/sky130A/libs.tech/ngspice/sky130.lib.spice" tt

* Power supply: 1.8V
Vdd vdd gnd 1.8



* Inputs
* PULSE(initial final delay rise fall widht period)
VinA inA gnd PULSE(0 1.8 10ns 100ps 100ps 10ns 20ns)
VinB inB gnd PULSE(0 1.8 15ns 100ps 100ps 10ns 20ns)

* Two PMOS transistors in parralel for the pull-up network  (W=1u, L=150n)
* Format: Mname drain gate source body model W=... L=...
Xp1 NAND inA vdd vdd sky130_fd_pr__pfet_01v8_hvt  l=0.150  w=0.99
Xp2 NAND inB vdd vdd sky130_fd_pr__pfet_01v8_hvt  l=0.150  w=0.99

* Two NMOS transistors in series for the pull-down network  (W=0.5u, L=150n)
Xn1 NAND inA npd gnd sky130_fd_pr__nfet_01v8  l=0.150  w=0.495
Xn2 npd  inB gnd gnd sky130_fd_pr__nfet_01v8  l=0.150  w=0.495

* Output load capacitor (typical gate load)
Cload NAND gnd 10f

* Simulation: transient analysis for 30ns
.tran 10p 30ns

* Save node voltages for plotting
.save v(inA) v(inB) v(NAND)

* Control block for ngspice
.control
run
plot v(inA) v(inB) v(NAND)
plot v(inA) v(NAND)
plot v(inB) v(NAND)
meas tran tpd_hl TRIG v(inA) VAL=0.9 RISE=1 TARG v(NAND) VAL=0.9 FALL=1
meas tran tpd_lh TRIG v(inA) VAL=0.9 FALL=1 TARG v(NAND) VAL=0.9 RISE=1
meas tran tpd_hl TRIG v(inB) VAL=0.9 RISE=1 TARG v(NAND) VAL=0.9 FALL=1
meas tran tpd_lh TRIG v(inB) VAL=0.9 FALL=1 TARG v(NAND) VAL=0.9 RISE=1

.endc

.end

Assignment3¶

Write an initial analog block that you can use in your chip project (e.g., an adder, counter, etc.)

I tried to make D-flipflop using Xscheme.

First I refered to (this page.)[https://www.build-electronic-circuits.com/d-flip-flop/] D-flip flop is showned as this diagram.

The location of the symbols in Xscheme¶

Standard parts

/usr/local/share/xschem/xschem_library/devices
Trangistor, resistor, capasitor for sky130

/home/user/pdk/sky130A/libs.tech/xschem/sky130_fd_pr
Digital parts for sky130(logic parts)

/home/user/pdk/sky130A/libs.tech/xschem/sky130_stdcells

I used following parts. - pin.sym - pout.sym - vdd.sym - gnd.sym - code_shown.sym - pfet_01v8.sym - nfet_01v8.sym