Session 03: Schematic Design & Simulation¶
In this session, we learned how to design the sechematic of the chip and how to simulate it with SPICE (Simulation Program with Integrated Circuit Emphasis).
Homework¶
- Reuse and.sp netlist, which has a 2-input AND gate to make a 2-input NAND gate (e.g., remove the output inverter) and change the models to refer to the PDK models
- Simulate it in SPICE, verify truth table (it will look something like the right table), and measure propagation delays (low-to-high and high-to-low)
- Write an initial analog block that you can use in your chip project (e.g., an adder, counter, etc.)
Schematic Design by Netlist¶
First, to get used to write netlist, I tried to copy by hand the sample code in the class page.
Then, run the ngspice. But the error occurs.
The output is:
Error on line 654 or its substitute:
m.xp.msky130_fd_pr__pfet_01v8 out in vdd vdd xp:sky130_fd_pr__pfet_01v8__model l= 1.500000000000000e-07 w= 1.000000000000000e-06 nf= 1.000000000000000e+00 ad= 0.000000000000000e+00 as= 0.000000000000000e+00 pd= 0.000000000000000e+00 ps= 0.000000000000000e+00 nrd= 0.000000000000000e+00 nrs= 0.000000000000000e+00 sa= 0.000000000000000e+00 sb= 0.000000000000000e+00 sd= 0.000000000000000e+00
could not find a valid modelname
Simulation interrupted due to error!
Um… it seems the unit of description for Width and Duration.
- l = 1.500000000000000e-07 millsec(?) = 0.15 nano-second(?)
- w = 1.000000000000000e-06 millsec(?) = 1.0 nano-second(?)
So, I modified the netlist as following:
* CMOS Inverter Simulation
* For Fab Futures - Week 2
* Include the Sky130 device models
.lib "../pdks/sky130A/libs.tech/ngspice/sky130.lib.spice" tt
* Power supply: 1.8V
Vdd vdd gnd 1.8
* Input: pulse from 0V to 1.8V
* PULSE(initial final delay rise fall width period)
Vin in gnd PULSE(0 1.8 1n 100p 100p 2n 4n)
* PMOS transistor (W=1u, L=150n)
* Format: Mname drain gate source body model W=... L=...
Xp out in vdd vdd sky130_fd_pr__pfet_01v8 W=0.99 L=0.150
* NMOS transistor (W=0.5u, L=150n)
Xn out in gnd gnd sky130_fd_pr__nfet_01v8 W=0.495 L=0.150
* Output load capacitor (typical gate load)
Cload out gnd 10f
* Simulation: transient analysis, 10ps step, 20ns duration
.tran 10p 20n
* Save node voltages for plotting
.save v(in) v(out)
* Control block for ngspice
.control
run
plot v(in) v(out)
meas tran tpd_hl TRIG v(in) VAL=0.9 RISE=1 TARG v(out) VAL=0.9 FALL=1
meas tran tpd_lh TRIG v(in) VAL=0.9 FALL=1 TARG v(out) VAL=0.9 RISE=1
.endc
Then, run the simulation.
The result show:
Note: No compatibility mode selected!
Circuit: * cmos inverter simulation
Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
Using SPARSE 1.3 as Direct Linear Solver
Initial Transient Solution
--------------------------
Node Voltage
---- -------
vdd 1.8
in 0
out 1.8
vin#branch 0
vdd#branch -1.91185e-12
Reference value : 1.98050e-08
No. of Data Rows : 2068
tpd_hl = 6.686341e-11 targ= 1.116863e-09 trig= 1.050000e-09
tpd_lh = 8.095573e-11 targ= 3.230956e-09 trig= 3.150000e-09
To save the result of simulation, added this code for CSV export.
.control
run
plot v(in) v(out)
meas tran tpd_hl TRIG v(in) VAL=0.9 RISE=1 TARG v(out) VAL=0.9 FALL=1
meas tran tpd_lh TRIG v(in) VAL=0.9 FALL=1 TARG v(out) VAL=0.9 RISE=1
wrdata result.csv v(in) v(out)
.endc
Then, run the ngspice and CSV file is exported.
And, write and run the python code.
import numpy as np
import matplotlib.pyplot as plt
data = np.loadtxt('result.csv')
time = data[:, 0]
v_out = data[:, 2]
plt.plot(time * 1e9, v_out)
plt.xlabel('Time(ns)')
plt.ylabel('Vout (V)')
plt.savefig('out.jpg')
It plots the csv data into the graph and save it as jpeg file.
Assignment 1: Schematic of 2 in NAND with PDK libraries¶
Reuse and.sp netlist, which has a 2-input AND gate to make a 2-input NAND gate (e.g., remove the output inverter) and change the models to refer to the PDK
I have struugle to the error “model does not exit” so much.... Finally I found out the description should be follow the library definitions. For example, if I want to define Voltage Input, for example inA, I should write first label As “VinX”. At the same time, if I want to define the PMOS, I should write XpX (Xp1, Xp2…). First, I wrote here as “Mp1” (following former and.sp netlist), that caused the error.
I modified and.sp netlist as following:
* AND Gate using CMOS
* Include the Sky130 device models
.lib "../pdks/sky130A/libs.tech/ngspice/sky130.lib.spice" tt
* Power supply
Vdd vdd gnd 1.8
* Input signals (PULSE)
VinA inA gnd PULSE(0 1.8 1n 100p 100p 2n 6n)
VinB inB gnd PULSE(0 1.8 1n 100p 100p 4n 10n)
* NAND gate
* PMOS pull-up (parallel)
Xp1 nand_out inA vdd vdd sky130_fd_pr__pfet_01v8 W=0.99 L=0.150
Xp2 nand_out inB vdd vdd sky130_fd_pr__pfet_01v8 W=0.99 L=0.150
*Mp1 nand_out a vdd vdd pmos L=1u W=2u
*Mp2 nand_out b vdd vdd pmos L=1u W=2u
* NMOS pull-down (serial)
Xn1 nand_out inA mid gnd sky130_fd_pr__nfet_01v8 W=0.495 L=0.150
Xn2 mid inB gnd gnd sky130_fd_pr__nfet_01v8 W=0.495 L=0.150
*Mn1 nand_out a mid gnd nmos L=1u W=2u
*Mn2 mid b gnd gnd nmos L=1u W=1u
* Output load capacitor
Cload nand_out gnd 10f
.tran 10p 20n
.save v(inA) v(inB) v(nand_out)
* Simulation control
.control
run
plot v(inA) v(inB) v(nand_out)
plot v(inA)
plot v(inB)
meas tran tpd_hl TRIG v(inA) VAL=0.9 RISE=1 TARG v(nand_out) VAL=0.9 FALL=1
meas tran tpd_lh TRIG v(inA) VAL=0.9 FALL=1 TARG v(nand_out) VAL=0.9 RISE=1
meas tran tpd_hl TRIG v(inB) VAL=0.9 RISE=1 TARG v(nand_out) VAL=0.9 FALL=1
meas tran tpd_lh TRIG v(inB) VAL=0.9 FALL=1 TARG v(nand_out) VAL=0.9 RISE=1
.endc
.end
Then, I got the result as follow:
Circuit: * and gate using cmos
Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
Using SPARSE 1.3 as Direct Linear Solver
Initial Transient Solution
--------------------------
Node Voltage
---- -------
vdd 1.8
ina 0
inb 0
nand_out 1.8
mid 0.019587
vinb#branch 0
vina#branch 0
vdd#branch -1.86185e-12
Reference value : 1.56050e-08
No. of Data Rows : 2062
tpd_hl = 1.036557e-10 targ= 1.153656e-09 trig= 1.050000e-09
tpd_lh = 8.251395e-11 targ= 3.232514e-09 trig= 3.150000e-09
tpd_hl = 1.036557e-10 targ= 1.153656e-09 trig= 1.050000e-09
tpd_lh = -1.917486e-09 targ= 3.232514e-09 trig= 5.150000e-09
Assignment 2: Simulation in SPICE¶
Simulate it in SPICE, verify truth table (it will look something like the right table)
The truth table of NAND is here:
| A | B | OUT |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
I wrote VinA as follow: input PULSE 2 nano second every 6 nano second.
VinA inA gnd PULSE(0 1.8 1n 100p 100p 2n 6n)
Also, I wrote VinB as follow: input PULSE 4 nano second every 10 second.
VinB inB gnd PULSE(0 1.8 1n 100p 100p 4n 10n)
The following is the graph of VinA between 0.0n ~ 20.0n.
The following is the graph of VinB between 0.0n ~ 20.0n.
The following is the graph of nand_out.
(I just modified the plot part as follow to find out the nand_out line more clearly)
plot v(inA) v(inB);3 v(nand_out)+6
The orange line, nand_out, show when both vina(red line) and vinb(blue line) are low, nand_out (orange line) would be low. Other situation, the orange line would be high. I could confirm the simulation follows the truth table.
measure propagation delays (low-to-high and high-to-low)
It takes time for the transistor to fully turn ON, and it takes time for the signal to be output after it is input. This time is called the propagation delay time. This is called as “propagation delay”.
Propagation delay would come out when the signal turn low to high or high to low.
(quated from the session 03 slide pdf)
The following is the graph of nand_out. If we focus to the time when the line reached to high or low and zoom in the graph, we can find this propagation delay.
These are the phase when the nand_out would turn to HIGH.
These are the phase when the nand_out would turn to LOW.
The following is the graph of VinA, VinB and nand_out. If we zoom in to the place where the vina turn into low and nand_out turn into HIGH, we can see the timing of nand_out is delay to HIGH.
Here is the measurment result:
tpd_hl = 1.036557e-10 targ= 1.153656e-09 trig= 1.050000e-09
tpd_lh = 8.251395e-11 targ= 3.232514e-09 trig= 3.150000e-09
tpd_hl = 1.036557e-10 targ= 1.153656e-09 trig= 1.050000e-09
tpd_lh = -1.917486e-09 targ= 3.232514e-09 trig= 5.150000e-09
Assignment 3: Initial Analog Block¶
Before starting section, I remember some taxnomy....
- Verilog: is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design and verification of digital circuits
- Verilog-A is an industry standard modeling language for analog circuits.
Write an initial analog block that you can use in your chip project (e.g., an adder, counter, etc.)
This article is very useful to start learning how to write verilog-a and how to simulate it (with thanks to Þórarinn).
First, I wrote the following Verilog-A code, that represented simple voltage amplifier.
`include "constants.vams"
`include "disciplines.vams"
module amplifier(in,out);
input in;
output out;
electrical in, out;
parameter real Gain = 1.0; // Default gain is 1.0
analog begin
// The output voltage is the input voltage multiplied by the gain
V(out) <+ Gain * V(in);
end
endmodule
Saved the filename as “hello.va”, Then, compile the verilog-A file. “hello.osdi” file are generated.
openvaf hello.va
Finished building hello.va in 0.03s
Then, include and use on the netlist:
* Include verilog-a model file
.model Amp amplifier PARAMS: Gain=1.5
* Define the sinusoidal input source:
* sin(Voffset Vamp Freq TD Theta Phase)
* Here: offset=0, amplitude=1V freq=1Hz no delay, no damping, no phase
VIN in 0 sin(0 1 1 0 0 0)
* Instantiate the Verilog-A amplifier:
* The Verilog-A module is named "hello" and we pass Gain=1.0 (optional)
NAMP in out Amp
** Simulation directives:
** We'll run a transient from t=0 to t=5s with a timestep of 0.01s
.tran 0.01 5
* controle statements:
.control
set wr_singlescale
set wr_vecnames
* Load the Verilog-A model (OSDI File)
pre_osdi hello.osdi
run
wrdata hello.txt V(in) V(out)
plot V(in) V(out)
.endc
.end
Then, run the ngspice simulation.
/foss/designs > ngspice test-hello.spice
Note: No compatibility mode selected!
Circuit: * include verilog-a model file
Warning: Model issue on line 2 :
.model amp amplifier params: gain=1.5 ...
unrecognized parameter (params:) - ignored
Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
Using SPARSE 1.3 as Direct Linear Solver
Initial Transient Solution
--------------------------
Node Voltage
---- -------
in 0
out 0
vin#branch 0
No. of Data Rows : 508
ngspice 2 ->
And, I could see the sin-wave graph using the amplifier. The graph show when the input voltage is 1.0 v, output voltage is amplified to 1.5v.
if the Gain is change to 2.0 as following:
.model Amp amplifier PARAMS: Gain=2.0
The output of the graph become 2.0v.
From this tutorial, I could understand
- Verilog-A: to design(write) a block (or parts?) of analog function in IC design. For example, ADC converter, Amplifier… and so on.
- Verilog: to design a function of digital logic (data flow between registers, register transfer level and so on).
- Netlist: to design the circuit of IC with including analog block and digital logic written by Verilog/Verilog-A.
As my first analog block, I choosed the binary counter which could be find out in this page.