Session 6: Synthesis & Physical Design¶
Project homework:¶
System overview¶
Prepare Makefile¶
I use that Makefile (inspired by the one provided in the class) for everything (lint, simulation, synthesis..) Easier than to remenber all paths and commands..
# =============================================================================
# Fab Futures - Philippe Libioulle - Build Automation
# =============================================================================
#
# Lint
# make lint-top - Lint top level
# make lint-puf - Lint 1bit PUF
# make lint-arbiter - Lint Arbiter
# make lint-counter - Lint Counter
# make lint-mux - Lint MUX
# make lint-ro - Lint RO
#
# Simulation (no special setup required):
# make sim-puf - Simulate entire PUF project
# make sim-arbiter - Simulate Arbiter
# make sim-counter - Simulate Counter
# make sim-mux - Simulate MUX
# make sim-ro - Simulate RO
##
# ASIC Flow (requires IIC-OSIC-TOOLS Docker environment):
# make build-puf - Full flow for PUF project#
# make view-puf - View PUF layout in KLayout
#
# Individual steps:
# make sky130-puf - Synthesize to Sky130 cells
# make pnr-puf - Place and route
# make gds-puf - Generate GDS
# make report-puf
#
# Setup:
# ASIC flow requires the Sky130 PDK. Use one of:
# 1. Run inside IIC-OSIC-TOOLS Docker (PDK_ROOT is set automatically)
# 2. Set PDK_ROOT manually: export PDK_ROOT=/path/to/pdks
#
# =============================================================================
# Default shell
SHELL := /bin/bash
# Tools
IVERILOG := iverilog
VVP := vvp
VERILATOR := verilator
YOSYS := yosys
OPENROAD := openroad
MAGIC := magic
KLAYOUT := klayout
# Common options
IVERILOG_FLAGS := -Wall -g2012
VERILATOR_FLAGS := --lint-only -Wall
# Library and flow paths
LIB := lib
FLOW := flow
# =============================================================================
# PDK Detection
# =============================================================================
# Try to find PDK_ROOT automatically. Check common locations:
# 1. Environment variable (if already set)
# 2. /foss/pdks (IIC-OSIC-TOOLS Docker container)
# 3. ~/pdks (common local install)
# 4. /opt/pdks (system install)
ifndef PDK_ROOT
ifneq (,$(wildcard /foss/pdks/sky130A))
PDK_ROOT := /foss/pdks
else ifneq (,$(wildcard $(HOME)/pdks/sky130A))
PDK_ROOT := $(HOME)/pdks
else ifneq (,$(wildcard /opt/pdks/sky130A))
PDK_ROOT := /opt/pdks
endif
endif
# Helper to check if PDK is available (used by ASIC targets)
define check_pdk
@if [ -z "$(PDK_ROOT)" ]; then \
echo "ERROR: PDK_ROOT is not set and Sky130 PDK not found."; \
echo ""; \
echo "To run the ASIC flow, you need the Sky130 PDK. Options:"; \
echo " 1. Use IIC-OSIC-TOOLS Docker (recommended):"; \
echo " cd ../IIC-OSIC-TOOLS && ./start_jupyter.sh"; \
echo " Then run make commands inside the container."; \
echo ""; \
echo " 2. Set PDK_ROOT manually:"; \
echo " export PDK_ROOT=/path/to/pdks"; \
echo ""; \
echo "Simulation targets (make sim-*) work without the PDK."; \
exit 1; \
fi
endef
# =============================================================================
# Project definitions
# =============================================================================
# PUF
PUF_TOP := puf_top
PUF_DIR := puf
PUF_SRC := $(PUF_DIR)/puf_top.v $(PUF_DIR)/puf_bit.v $(PUF_DIR)/ro.v $(PUF_DIR)/mux.v $(PUF_DIR)/counter.v $(PUF_DIR)/arbiter.v
#/foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
#/foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v
PUF_BUILD := $(PUF_DIR)/build
# =============================================================================
# Simulation targets
# =============================================================================
.PHONY: sim-puf
sim-puf: $(PUF_DIR)/puf.vvp
$(VVP) $<
$(PUF_DIR)/puf.vvp: $(PUF_DIR)/puf_bit.v $(PUF_DIR)/ro.v $(PUF_DIR)/mux.v $(PUF_DIR)/counter.v $(PUF_DIR)/arbiter.v $(PUF_DIR)/test_puf_bit.v /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v
$(IVERILOG) $(IVERILOG_FLAGS) -I$(LIB) -o $@ $^
sim-arbiter: $(PUF_DIR)/arbiter.vvp
$(VVP) $<
$(PUF_DIR)/arbiter.vvp: $(PUF_DIR)/arbiter.v $(PUF_DIR)/test_arbiter.v
$(IVERILOG) $(IVERILOG_FLAGS) -I$(LIB) -o $@ $^
sim-mux: $(PUF_DIR)/mux.vvp
$(VVP) $<
$(PUF_DIR)/mux.vvp: $(PUF_DIR)/mux.v $(PUF_DIR)/test_mux.v
$(IVERILOG) $(IVERILOG_FLAGS) -I$(LIB) -o $@ $^
sim-counter: $(PUF_DIR)/counter.vvp
$(VVP) $<
$(PUF_DIR)/counter.vvp: $(PUF_DIR)/counter.v $(PUF_DIR)/test_counter.v
$(IVERILOG) $(IVERILOG_FLAGS) -I$(LIB) -o $@ $^
sim-ro: $(PUF_DIR)/ro.vvp
$(VVP) $<
$(PUF_DIR)/ro.vvp: $(PUF_DIR)/ro.v $(PUF_DIR)/test_ro.v /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v
$(IVERILOG) $(IVERILOG_FLAGS) -I$(LIB) -o $@ $^
# =============================================================================
# Lint targets
# =============================================================================
.PHONY: lint-puf
lint-top:
$(VERILATOR) $(VERILATOR_FLAGS) -I$(LIB) $(PUF_SRC) config.vlt
lint-puf:
$(VERILATOR) $(VERILATOR_FLAGS) -I$(LIB) $(PUF_DIR)/puf_bit.v
lint-arbiter:
$(VERILATOR) $(VERILATOR_FLAGS) -I$(LIB) $(PUF_DIR)/arbiter.v
lint-mux:
$(VERILATOR) $(VERILATOR_FLAGS) -I$(LIB) $(PUF_DIR)/mux.v
lint-counter:
$(VERILATOR) $(VERILATOR_FLAGS) -I$(LIB) $(PUF_DIR)/counter.v
lint-ro:
$(VERILATOR) $(VERILATOR_FLAGS) -I$(LIB) $(PUF_DIR)/ro.v config.vlt
# =============================================================================
# Quick synthesis (gate count only, no PDK required)
# =============================================================================
.PHONY: synth-puf
synth-puf:
$(YOSYS) -p "read_liberty -lib /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib; write_verilog -blackboxes sky130_blackboxes.v"
$(YOSYS) -p "read_verilog -D SYNTHESIS puf/puf_top.v puf/puf_bit.v puf/ro.v puf/arbiter.v puf/mux.v puf/counter.v ; read_verilog -lib sky130_blackboxes.v; hierarchy -top puf_top; proc; opt; techmap; opt; dfflibmap -liberty /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib; abc -liberty /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib; clean; stat; write_verilog -noattr $(PUF_BUILD)/$(PUF_TOP)_synth.v"
# =============================================================================
# ASIC Flow: Sky130 Synthesis
# =============================================================================
.PHONY: sky130-puf
sky130-puf: $(PUF_BUILD)/$(PUF_TOP)_synth.v
$(PUF_BUILD)/$(PUF_TOP)_synth.v: $(PUF_SRC)
$(call check_pdk)
@mkdir -p $(PUF_BUILD)
cd $(PUF_DIR) && \
TOP=$(PUF_TOP) \
VERILOG="$(PUF_SRC)" \
OUT_DIR=build \
$(YOSYS) -c ../$(FLOW)/synth.tcl
# =============================================================================
# ASIC Flow: Place & Route
# =============================================================================
.PHONY: pnr-puf
pnr-puf: $(PUF_BUILD)/$(PUF_TOP).def
$(PUF_BUILD)/$(PUF_TOP).def: $(PUF_BUILD)/$(PUF_TOP)_synth.v
cd $(PUF_DIR) && TOP=$(PUF_TOP) OUT_DIR=build $(OPENROAD) -exit ../$(FLOW)/pnr.tcl
# =============================================================================
# ASIC Flow: GDS Generation
# =============================================================================
.PHONY: gds-puf
gds-puf: $(PUF_BUILD)/$(PUF_TOP).gds
# GDS generation using KLayout
$(PUF_BUILD)/$(PUF_TOP).gds: $(PUF_BUILD)/$(PUF_TOP).def
cd $(PUF_DIR) && $(KLAYOUT) -zz -r ../$(FLOW)/def2gds.rb \
-rd def_file=build/$(PUF_TOP).def -rd gds_file=build/$(PUF_TOP).gds
# =============================================================================
# Full build targets
# =============================================================================
.PHONY: build-puf
build-puf: gds-puf
@echo "PUF build complete: $(PUF_BUILD)/$(PUF_TOP).gds"
# =============================================================================
# View layouts in KLayout
# =============================================================================
# KLayout can read DEF files directly with the LEF files for cell definitions
.PHONY: view-puf
LIB_DIR = $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd
view-puf: $(PUF_BUILD)/$(PUF_TOP).def
$(KLAYOUT) -nn $(PDK_ROOT)/sky130A/libs.tech/klayout/tech/sky130A.lyt \
$(LIB_DIR)/gds/sky130_fd_sc_hd.gds $<
# =============================================================================
# Reports
# =============================================================================
.PHONY: report-puf
report-puf:
@echo "=== PUF Reports ==="
@cat $(PUF_BUILD)/$(PUF_TOP)_timing.rpt 2>/dev/null || echo "Run 'make pnr-puf' first"
# =============================================================================
# Clean
# =============================================================================
.PHONY: clean clean-sim clean-build
clean-sim:
rm -f */*.vvp */*.vcd
@echo "Cleaned simulation files."
clean-build:
rm -rf */build
@echo "Cleaned build directories."
clean: clean-sim clean-build
@echo "All cleaned."
# =============================================================================
# Environment Check
# =============================================================================
.PHONY: check-env
check-env:
@echo "=== Environment Check ==="
@echo ""
@echo "PDK_ROOT: $(PDK_ROOT)"
@if [ -n "$(PDK_ROOT)" ] && [ -d "$(PDK_ROOT)/sky130A" ]; then \
echo " Status: OK (Sky130 PDK found)"; \
else \
echo " Status: NOT FOUND"; \
echo ""; \
echo " To use the ASIC flow, run inside IIC-OSIC-TOOLS Docker:"; \
echo " cd ../IIC-OSIC-TOOLS && ./start_jupyter.sh"; \
fi
@echo ""
@echo "Tools:"
@which $(YOSYS) > /dev/null 2>&1 && echo " yosys: OK ($(shell which $(YOSYS)))" || echo " yosys: NOT FOUND"
@which $(OPENROAD) > /dev/null 2>&1 && echo " openroad: OK ($(shell which $(OPENROAD)))" || echo " openroad: NOT FOUND"
@which $(MAGIC) > /dev/null 2>&1 && echo " magic: OK ($(shell which $(MAGIC)))" || echo " magic: NOT FOUND"
@which $(KLAYOUT) > /dev/null 2>&1 && echo " klayout: OK ($(shell which $(KLAYOUT)))" || echo " klayout: NOT FOUND"
@which $(IVERILOG) > /dev/null 2>&1 && echo " iverilog: OK ($(shell which $(IVERILOG)))" || echo " iverilog: NOT FOUND"
@which $(VERILATOR) > /dev/null 2>&1 && echo " verilator: OK ($(shell which $(VERILATOR)))" || echo " verilator: NOT FOUND"
@echo ""
# =============================================================================
# Help
# =============================================================================
.PHONY: help
help:
@echo "Fab Futures Examples Makefile"
@echo ""
@echo "Setup:"
@echo " make check-env - Check if tools and PDK are available"
@echo ""
@echo "Simulation (no PDK required):"
@echo " make sim-puf - Run PUF simulation"
@echo ""
@echo "Linting (no PDK required):"
@echo " make lint-puf - Lint PUF project with Verilator"
@echo ""
@echo "Quick Synthesis (no PDK required):"
@echo " make synth-puf - Synthesize and show gate count"
@echo ""
@echo "ASIC Flow (requires Sky130 PDK - run 'make check-env' to verify):"
@echo " make build-puf - Full flow: synth -> P&R -> GDS"
@echo ""
@echo "Individual ASIC steps:"
@echo " make sky130-puf - Synthesize to Sky130 cells"
@echo " make pnr-puf - Place and route"
@echo " make gds-puf - Generate GDS"
@echo ""
@echo "View & Reports:"
@echo " make view-puf - Open layout in KLayout"
@echo " make report-puf - Show timing/area reports"
@echo ""
@echo "Cleanup:"
@echo " make clean - Remove all generated files"
@echo " make clean-sim - Remove simulation files only"
@echo " make clean-build - Remove build directories only"
Here is the config.vlt file. The idea is to hide things I cannot do anything to fix and to display only warnings I could deal with. There are two ways to do this, either in your Verilog, for a specific part of your code, or at the configuration file level, for a set of modules
// Turn off all warnings for Sky130 files
`verilator_config lint_off -rule SPECIFYIGN -file "/foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
`verilator_config lint_off -rule DECLFILENAME -file "/foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
`verilator_config lint_off -rule DECLFILENAME -file "/foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
`verilator_config lint_off -rule SPECIFYIGN -file "/foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
Prepare sources¶
Lint first¶
make lint-top
/foss/designs/philippelibioulle/designs > make lint-top
verilator --lint-only -Wall -Ilib puf/puf_bit.v puf/ro.v puf/mux.v puf/counter.v puf/arbiter.v puf/puf_top.v config.vlt
- V e r i l a t i o n R e p o r t: Verilator 5.044 2026-01-01 rev v5.044
- Verilator: Built from 0.131 MB sources in 7 modules, into 23.107 MB in 26 C++ files needing 0.000 MB
- Verilator: Walltime 1.591 s (elab=0.003, cvt=1.261, bld=0.000); cpu 1.591 s on 1 threads; alloced 233.344 MB
Synthesize your design - review gate count, check for unintended latches¶
mkdir puf/build
make synth-puf
yosys -p "read_liberty -lib /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib; write_verilog -blackboxes sky130_blackboxes.v"
/----------------------------------------------------------------------------\
| yosys -- Yosys Open SYnthesis Suite |
| Copyright (C) 2012 - 2026 Claire Xenia Wolf <claire@yosyshq.com> |
| Distributed under an ISC-like license, type "license" to see terms |
\----------------------------------------------------------------------------/
Yosys 0.62 (git sha1 7326bb7d6, g++ 13.3.0-6ubuntu2~24.04 -fPIC -O3)
-- Running command `read_liberty -lib /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib; write_verilog -blackboxes sky130_blackboxes.v' --
1. Executing Liberty frontend: /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
Imported 428 cell types from liberty file.
2. Executing Verilog backend.
2.1. Executing BMUXMAP pass.
2.2. Executing DEMUXMAP pass.
Dumping module `\sky130_fd_sc_hd__a2111o_1'.
Dumping module `\sky130_fd_sc_hd__a2111o_2'.
Dumping module `\sky130_fd_sc_hd__a2111o_4'.
Dumping module `\sky130_fd_sc_hd__a2111oi_0'.
Dumping module `\sky130_fd_sc_hd__a2111oi_1'.
Dumping module `\sky130_fd_sc_hd__a2111oi_2'.
Dumping module `\sky130_fd_sc_hd__a2111oi_4'.
Dumping module `\sky130_fd_sc_hd__a211o_1'.
Dumping module `\sky130_fd_sc_hd__a211o_2'.
Dumping module `\sky130_fd_sc_hd__a211o_4'.
Dumping module `\sky130_fd_sc_hd__a211oi_1'.
Dumping module `\sky130_fd_sc_hd__a211oi_2'.
Dumping module `\sky130_fd_sc_hd__a211oi_4'.
Dumping module `\sky130_fd_sc_hd__a21bo_1'.
Dumping module `\sky130_fd_sc_hd__a21bo_2'.
Dumping module `\sky130_fd_sc_hd__a21bo_4'.
Dumping module `\sky130_fd_sc_hd__a21boi_0'.
Dumping module `\sky130_fd_sc_hd__a21boi_1'.
Dumping module `\sky130_fd_sc_hd__a21boi_2'.
Dumping module `\sky130_fd_sc_hd__a21boi_4'.
Dumping module `\sky130_fd_sc_hd__a21o_1'.
Dumping module `\sky130_fd_sc_hd__a21o_2'.
Dumping module `\sky130_fd_sc_hd__a21o_4'.
Dumping module `\sky130_fd_sc_hd__a21oi_1'.
Dumping module `\sky130_fd_sc_hd__a21oi_2'.
Dumping module `\sky130_fd_sc_hd__a21oi_4'.
Dumping module `\sky130_fd_sc_hd__a221o_1'.
Dumping module `\sky130_fd_sc_hd__a221o_2'.
Dumping module `\sky130_fd_sc_hd__a221o_4'.
Dumping module `\sky130_fd_sc_hd__a221oi_1'.
Dumping module `\sky130_fd_sc_hd__a221oi_2'.
Dumping module `\sky130_fd_sc_hd__a221oi_4'.
Dumping module `\sky130_fd_sc_hd__a222oi_1'.
Dumping module `\sky130_fd_sc_hd__a22o_1'.
Dumping module `\sky130_fd_sc_hd__a22o_2'.
Dumping module `\sky130_fd_sc_hd__a22o_4'.
Dumping module `\sky130_fd_sc_hd__a22oi_1'.
Dumping module `\sky130_fd_sc_hd__a22oi_2'.
Dumping module `\sky130_fd_sc_hd__a22oi_4'.
Dumping module `\sky130_fd_sc_hd__a2bb2o_1'.
Dumping module `\sky130_fd_sc_hd__a2bb2o_2'.
Dumping module `\sky130_fd_sc_hd__a2bb2o_4'.
Dumping module `\sky130_fd_sc_hd__a2bb2oi_1'.
Dumping module `\sky130_fd_sc_hd__a2bb2oi_2'.
Dumping module `\sky130_fd_sc_hd__a2bb2oi_4'.
Dumping module `\sky130_fd_sc_hd__a311o_1'.
Dumping module `\sky130_fd_sc_hd__a311o_2'.
Dumping module `\sky130_fd_sc_hd__a311o_4'.
Dumping module `\sky130_fd_sc_hd__a311oi_1'.
Dumping module `\sky130_fd_sc_hd__a311oi_2'.
Dumping module `\sky130_fd_sc_hd__a311oi_4'.
Dumping module `\sky130_fd_sc_hd__a31o_1'.
Dumping module `\sky130_fd_sc_hd__a31o_2'.
Dumping module `\sky130_fd_sc_hd__a31o_4'.
Dumping module `\sky130_fd_sc_hd__a31oi_1'.
Dumping module `\sky130_fd_sc_hd__a31oi_2'.
Dumping module `\sky130_fd_sc_hd__a31oi_4'.
Dumping module `\sky130_fd_sc_hd__a32o_1'.
Dumping module `\sky130_fd_sc_hd__a32o_2'.
Dumping module `\sky130_fd_sc_hd__a32o_4'.
Dumping module `\sky130_fd_sc_hd__a32oi_1'.
Dumping module `\sky130_fd_sc_hd__a32oi_2'.
Dumping module `\sky130_fd_sc_hd__a32oi_4'.
Dumping module `\sky130_fd_sc_hd__a41o_1'.
Dumping module `\sky130_fd_sc_hd__a41o_2'.
Dumping module `\sky130_fd_sc_hd__a41o_4'.
Dumping module `\sky130_fd_sc_hd__a41oi_1'.
Dumping module `\sky130_fd_sc_hd__a41oi_2'.
Dumping module `\sky130_fd_sc_hd__a41oi_4'.
Dumping module `\sky130_fd_sc_hd__and2_0'.
Dumping module `\sky130_fd_sc_hd__and2_1'.
Dumping module `\sky130_fd_sc_hd__and2_2'.
Dumping module `\sky130_fd_sc_hd__and2_4'.
Dumping module `\sky130_fd_sc_hd__and2b_1'.
Dumping module `\sky130_fd_sc_hd__and2b_2'.
Dumping module `\sky130_fd_sc_hd__and2b_4'.
Dumping module `\sky130_fd_sc_hd__and3_1'.
Dumping module `\sky130_fd_sc_hd__and3_2'.
Dumping module `\sky130_fd_sc_hd__and3_4'.
Dumping module `\sky130_fd_sc_hd__and3b_1'.
Dumping module `\sky130_fd_sc_hd__and3b_2'.
Dumping module `\sky130_fd_sc_hd__and3b_4'.
Dumping module `\sky130_fd_sc_hd__and4_1'.
Dumping module `\sky130_fd_sc_hd__and4_2'.
Dumping module `\sky130_fd_sc_hd__and4_4'.
Dumping module `\sky130_fd_sc_hd__and4b_1'.
Dumping module `\sky130_fd_sc_hd__and4b_2'.
Dumping module `\sky130_fd_sc_hd__and4b_4'.
Dumping module `\sky130_fd_sc_hd__and4bb_1'.
Dumping module `\sky130_fd_sc_hd__and4bb_2'.
Dumping module `\sky130_fd_sc_hd__and4bb_4'.
Dumping module `\sky130_fd_sc_hd__buf_1'.
Dumping module `\sky130_fd_sc_hd__buf_12'.
Dumping module `\sky130_fd_sc_hd__buf_16'.
Dumping module `\sky130_fd_sc_hd__buf_2'.
Dumping module `\sky130_fd_sc_hd__buf_4'.
Dumping module `\sky130_fd_sc_hd__buf_6'.
Dumping module `\sky130_fd_sc_hd__buf_8'.
Dumping module `\sky130_fd_sc_hd__bufbuf_16'.
Dumping module `\sky130_fd_sc_hd__bufbuf_8'.
Dumping module `\sky130_fd_sc_hd__bufinv_16'.
Dumping module `\sky130_fd_sc_hd__bufinv_8'.
Dumping module `\sky130_fd_sc_hd__clkbuf_1'.
Dumping module `\sky130_fd_sc_hd__clkbuf_16'.
Dumping module `\sky130_fd_sc_hd__clkbuf_2'.
Dumping module `\sky130_fd_sc_hd__clkbuf_4'.
Dumping module `\sky130_fd_sc_hd__clkbuf_8'.
Dumping module `\sky130_fd_sc_hd__clkdlybuf4s15_1'.
Dumping module `\sky130_fd_sc_hd__clkdlybuf4s15_2'.
Dumping module `\sky130_fd_sc_hd__clkdlybuf4s18_1'.
Dumping module `\sky130_fd_sc_hd__clkdlybuf4s18_2'.
Dumping module `\sky130_fd_sc_hd__clkdlybuf4s25_1'.
Dumping module `\sky130_fd_sc_hd__clkdlybuf4s25_2'.
Dumping module `\sky130_fd_sc_hd__clkdlybuf4s50_1'.
Dumping module `\sky130_fd_sc_hd__clkdlybuf4s50_2'.
Dumping module `\sky130_fd_sc_hd__clkinv_1'.
Dumping module `\sky130_fd_sc_hd__clkinv_16'.
Dumping module `\sky130_fd_sc_hd__clkinv_2'.
Dumping module `\sky130_fd_sc_hd__clkinv_4'.
Dumping module `\sky130_fd_sc_hd__clkinv_8'.
Dumping module `\sky130_fd_sc_hd__clkinvlp_2'.
Dumping module `\sky130_fd_sc_hd__clkinvlp_4'.
Dumping module `\sky130_fd_sc_hd__conb_1'.
Dumping module `\sky130_fd_sc_hd__decap_12'.
Dumping module `\sky130_fd_sc_hd__decap_3'.
Dumping module `\sky130_fd_sc_hd__decap_4'.
Dumping module `\sky130_fd_sc_hd__decap_6'.
Dumping module `\sky130_fd_sc_hd__decap_8'.
Dumping module `\sky130_fd_sc_hd__dfbbn_1'.
Dumping module `\sky130_fd_sc_hd__dfbbn_2'.
Dumping module `\sky130_fd_sc_hd__dfbbp_1'.
Dumping module `\sky130_fd_sc_hd__dfrbp_1'.
Dumping module `\sky130_fd_sc_hd__dfrbp_2'.
Dumping module `\sky130_fd_sc_hd__dfrtn_1'.
Dumping module `\sky130_fd_sc_hd__dfrtp_1'.
Dumping module `\sky130_fd_sc_hd__dfrtp_2'.
Dumping module `\sky130_fd_sc_hd__dfrtp_4'.
Dumping module `\sky130_fd_sc_hd__dfsbp_1'.
Dumping module `\sky130_fd_sc_hd__dfsbp_2'.
Dumping module `\sky130_fd_sc_hd__dfstp_1'.
Dumping module `\sky130_fd_sc_hd__dfstp_2'.
Dumping module `\sky130_fd_sc_hd__dfstp_4'.
Dumping module `\sky130_fd_sc_hd__dfxbp_1'.
Dumping module `\sky130_fd_sc_hd__dfxbp_2'.
Dumping module `\sky130_fd_sc_hd__dfxtp_1'.
Dumping module `\sky130_fd_sc_hd__dfxtp_2'.
Dumping module `\sky130_fd_sc_hd__dfxtp_4'.
Dumping module `\sky130_fd_sc_hd__diode_2'.
Dumping module `\sky130_fd_sc_hd__dlclkp_1'.
Dumping module `\sky130_fd_sc_hd__dlclkp_2'.
Dumping module `\sky130_fd_sc_hd__dlclkp_4'.
Dumping module `\sky130_fd_sc_hd__dlrbn_1'.
Dumping module `\sky130_fd_sc_hd__dlrbn_2'.
Dumping module `\sky130_fd_sc_hd__dlrbp_1'.
Dumping module `\sky130_fd_sc_hd__dlrbp_2'.
Dumping module `\sky130_fd_sc_hd__dlrtn_1'.
Dumping module `\sky130_fd_sc_hd__dlrtn_2'.
Dumping module `\sky130_fd_sc_hd__dlrtn_4'.
Dumping module `\sky130_fd_sc_hd__dlrtp_1'.
Dumping module `\sky130_fd_sc_hd__dlrtp_2'.
Dumping module `\sky130_fd_sc_hd__dlrtp_4'.
Dumping module `\sky130_fd_sc_hd__dlxbn_1'.
Dumping module `\sky130_fd_sc_hd__dlxbn_2'.
Dumping module `\sky130_fd_sc_hd__dlxbp_1'.
Dumping module `\sky130_fd_sc_hd__dlxtn_1'.
Dumping module `\sky130_fd_sc_hd__dlxtn_2'.
Dumping module `\sky130_fd_sc_hd__dlxtn_4'.
Dumping module `\sky130_fd_sc_hd__dlxtp_1'.
Dumping module `\sky130_fd_sc_hd__dlygate4sd1_1'.
Dumping module `\sky130_fd_sc_hd__dlygate4sd2_1'.
Dumping module `\sky130_fd_sc_hd__dlygate4sd3_1'.
Dumping module `\sky130_fd_sc_hd__dlymetal6s2s_1'.
Dumping module `\sky130_fd_sc_hd__dlymetal6s4s_1'.
Dumping module `\sky130_fd_sc_hd__dlymetal6s6s_1'.
Dumping module `\sky130_fd_sc_hd__ebufn_1'.
Dumping module `\sky130_fd_sc_hd__ebufn_2'.
Dumping module `\sky130_fd_sc_hd__ebufn_4'.
Dumping module `\sky130_fd_sc_hd__ebufn_8'.
Dumping module `\sky130_fd_sc_hd__edfxbp_1'.
Dumping module `\sky130_fd_sc_hd__edfxtp_1'.
Dumping module `\sky130_fd_sc_hd__einvn_0'.
Dumping module `\sky130_fd_sc_hd__einvn_1'.
Dumping module `\sky130_fd_sc_hd__einvn_2'.
Dumping module `\sky130_fd_sc_hd__einvn_4'.
Dumping module `\sky130_fd_sc_hd__einvn_8'.
Dumping module `\sky130_fd_sc_hd__einvp_1'.
Dumping module `\sky130_fd_sc_hd__einvp_2'.
Dumping module `\sky130_fd_sc_hd__einvp_4'.
Dumping module `\sky130_fd_sc_hd__einvp_8'.
Dumping module `\sky130_fd_sc_hd__fa_1'.
Dumping module `\sky130_fd_sc_hd__fa_2'.
Dumping module `\sky130_fd_sc_hd__fa_4'.
Dumping module `\sky130_fd_sc_hd__fah_1'.
Dumping module `\sky130_fd_sc_hd__fahcin_1'.
Dumping module `\sky130_fd_sc_hd__fahcon_1'.
Dumping module `\sky130_fd_sc_hd__ha_1'.
Dumping module `\sky130_fd_sc_hd__ha_2'.
Dumping module `\sky130_fd_sc_hd__ha_4'.
Dumping module `\sky130_fd_sc_hd__inv_1'.
Dumping module `\sky130_fd_sc_hd__inv_12'.
Dumping module `\sky130_fd_sc_hd__inv_16'.
Dumping module `\sky130_fd_sc_hd__inv_2'.
Dumping module `\sky130_fd_sc_hd__inv_4'.
Dumping module `\sky130_fd_sc_hd__inv_6'.
Dumping module `\sky130_fd_sc_hd__inv_8'.
Dumping module `\sky130_fd_sc_hd__lpflow_bleeder_1'.
Dumping module `\sky130_fd_sc_hd__lpflow_clkbufkapwr_1'.
Dumping module `\sky130_fd_sc_hd__lpflow_clkbufkapwr_16'.
Dumping module `\sky130_fd_sc_hd__lpflow_clkbufkapwr_2'.
Dumping module `\sky130_fd_sc_hd__lpflow_clkbufkapwr_4'.
Dumping module `\sky130_fd_sc_hd__lpflow_clkbufkapwr_8'.
Dumping module `\sky130_fd_sc_hd__lpflow_clkinvkapwr_1'.
Dumping module `\sky130_fd_sc_hd__lpflow_clkinvkapwr_16'.
Dumping module `\sky130_fd_sc_hd__lpflow_clkinvkapwr_2'.
Dumping module `\sky130_fd_sc_hd__lpflow_clkinvkapwr_4'.
Dumping module `\sky130_fd_sc_hd__lpflow_clkinvkapwr_8'.
Dumping module `\sky130_fd_sc_hd__lpflow_decapkapwr_12'.
Dumping module `\sky130_fd_sc_hd__lpflow_decapkapwr_3'.
Dumping module `\sky130_fd_sc_hd__lpflow_decapkapwr_4'.
Dumping module `\sky130_fd_sc_hd__lpflow_decapkapwr_6'.
Dumping module `\sky130_fd_sc_hd__lpflow_decapkapwr_8'.
Dumping module `\sky130_fd_sc_hd__lpflow_inputiso0n_1'.
Dumping module `\sky130_fd_sc_hd__lpflow_inputiso0p_1'.
Dumping module `\sky130_fd_sc_hd__lpflow_inputiso1n_1'.
Dumping module `\sky130_fd_sc_hd__lpflow_inputiso1p_1'.
Dumping module `\sky130_fd_sc_hd__lpflow_inputisolatch_1'.
Dumping module `\sky130_fd_sc_hd__lpflow_isobufsrc_1'.
Dumping module `\sky130_fd_sc_hd__lpflow_isobufsrc_16'.
Dumping module `\sky130_fd_sc_hd__lpflow_isobufsrc_2'.
Dumping module `\sky130_fd_sc_hd__lpflow_isobufsrc_4'.
Dumping module `\sky130_fd_sc_hd__lpflow_isobufsrc_8'.
Dumping module `\sky130_fd_sc_hd__lpflow_isobufsrckapwr_16'.
Dumping module `\sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1'.
Dumping module `\sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2'.
Dumping module `\sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4'.
Dumping module `\sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_4'.
Dumping module `\sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1'.
Dumping module `\sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2'.
Dumping module `\sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4'.
Dumping module `\sky130_fd_sc_hd__macro_sparecell'.
Dumping module `\sky130_fd_sc_hd__maj3_1'.
Dumping module `\sky130_fd_sc_hd__maj3_2'.
Dumping module `\sky130_fd_sc_hd__maj3_4'.
Dumping module `\sky130_fd_sc_hd__mux2_1'.
Dumping module `\sky130_fd_sc_hd__mux2_2'.
Dumping module `\sky130_fd_sc_hd__mux2_4'.
Dumping module `\sky130_fd_sc_hd__mux2_8'.
Dumping module `\sky130_fd_sc_hd__mux2i_1'.
Dumping module `\sky130_fd_sc_hd__mux2i_2'.
Dumping module `\sky130_fd_sc_hd__mux2i_4'.
Dumping module `\sky130_fd_sc_hd__mux4_1'.
Dumping module `\sky130_fd_sc_hd__mux4_2'.
Dumping module `\sky130_fd_sc_hd__mux4_4'.
Dumping module `\sky130_fd_sc_hd__nand2_1'.
Dumping module `\sky130_fd_sc_hd__nand2_2'.
Dumping module `\sky130_fd_sc_hd__nand2_4'.
Dumping module `\sky130_fd_sc_hd__nand2_8'.
Dumping module `\sky130_fd_sc_hd__nand2b_1'.
Dumping module `\sky130_fd_sc_hd__nand2b_2'.
Dumping module `\sky130_fd_sc_hd__nand2b_4'.
Dumping module `\sky130_fd_sc_hd__nand3_1'.
Dumping module `\sky130_fd_sc_hd__nand3_2'.
Dumping module `\sky130_fd_sc_hd__nand3_4'.
Dumping module `\sky130_fd_sc_hd__nand3b_1'.
Dumping module `\sky130_fd_sc_hd__nand3b_2'.
Dumping module `\sky130_fd_sc_hd__nand3b_4'.
Dumping module `\sky130_fd_sc_hd__nand4_1'.
Dumping module `\sky130_fd_sc_hd__nand4_2'.
Dumping module `\sky130_fd_sc_hd__nand4_4'.
Dumping module `\sky130_fd_sc_hd__nand4b_1'.
Dumping module `\sky130_fd_sc_hd__nand4b_2'.
Dumping module `\sky130_fd_sc_hd__nand4b_4'.
Dumping module `\sky130_fd_sc_hd__nand4bb_1'.
Dumping module `\sky130_fd_sc_hd__nand4bb_2'.
Dumping module `\sky130_fd_sc_hd__nand4bb_4'.
Dumping module `\sky130_fd_sc_hd__nor2_1'.
Dumping module `\sky130_fd_sc_hd__nor2_2'.
Dumping module `\sky130_fd_sc_hd__nor2_4'.
Dumping module `\sky130_fd_sc_hd__nor2_8'.
Dumping module `\sky130_fd_sc_hd__nor2b_1'.
Dumping module `\sky130_fd_sc_hd__nor2b_2'.
Dumping module `\sky130_fd_sc_hd__nor2b_4'.
Dumping module `\sky130_fd_sc_hd__nor3_1'.
Dumping module `\sky130_fd_sc_hd__nor3_2'.
Dumping module `\sky130_fd_sc_hd__nor3_4'.
Dumping module `\sky130_fd_sc_hd__nor3b_1'.
Dumping module `\sky130_fd_sc_hd__nor3b_2'.
Dumping module `\sky130_fd_sc_hd__nor3b_4'.
Dumping module `\sky130_fd_sc_hd__nor4_1'.
Dumping module `\sky130_fd_sc_hd__nor4_2'.
Dumping module `\sky130_fd_sc_hd__nor4_4'.
Dumping module `\sky130_fd_sc_hd__nor4b_1'.
Dumping module `\sky130_fd_sc_hd__nor4b_2'.
Dumping module `\sky130_fd_sc_hd__nor4b_4'.
Dumping module `\sky130_fd_sc_hd__nor4bb_1'.
Dumping module `\sky130_fd_sc_hd__nor4bb_2'.
Dumping module `\sky130_fd_sc_hd__nor4bb_4'.
Dumping module `\sky130_fd_sc_hd__o2111a_1'.
Dumping module `\sky130_fd_sc_hd__o2111a_2'.
Dumping module `\sky130_fd_sc_hd__o2111a_4'.
Dumping module `\sky130_fd_sc_hd__o2111ai_1'.
Dumping module `\sky130_fd_sc_hd__o2111ai_2'.
Dumping module `\sky130_fd_sc_hd__o2111ai_4'.
Dumping module `\sky130_fd_sc_hd__o211a_1'.
Dumping module `\sky130_fd_sc_hd__o211a_2'.
Dumping module `\sky130_fd_sc_hd__o211a_4'.
Dumping module `\sky130_fd_sc_hd__o211ai_1'.
Dumping module `\sky130_fd_sc_hd__o211ai_2'.
Dumping module `\sky130_fd_sc_hd__o211ai_4'.
Dumping module `\sky130_fd_sc_hd__o21a_1'.
Dumping module `\sky130_fd_sc_hd__o21a_2'.
Dumping module `\sky130_fd_sc_hd__o21a_4'.
Dumping module `\sky130_fd_sc_hd__o21ai_0'.
Dumping module `\sky130_fd_sc_hd__o21ai_1'.
Dumping module `\sky130_fd_sc_hd__o21ai_2'.
Dumping module `\sky130_fd_sc_hd__o21ai_4'.
Dumping module `\sky130_fd_sc_hd__o21ba_1'.
Dumping module `\sky130_fd_sc_hd__o21ba_2'.
Dumping module `\sky130_fd_sc_hd__o21ba_4'.
Dumping module `\sky130_fd_sc_hd__o21bai_1'.
Dumping module `\sky130_fd_sc_hd__o21bai_2'.
Dumping module `\sky130_fd_sc_hd__o21bai_4'.
Dumping module `\sky130_fd_sc_hd__o221a_1'.
Dumping module `\sky130_fd_sc_hd__o221a_2'.
Dumping module `\sky130_fd_sc_hd__o221a_4'.
Dumping module `\sky130_fd_sc_hd__o221ai_1'.
Dumping module `\sky130_fd_sc_hd__o221ai_2'.
Dumping module `\sky130_fd_sc_hd__o221ai_4'.
Dumping module `\sky130_fd_sc_hd__o22a_1'.
Dumping module `\sky130_fd_sc_hd__o22a_2'.
Dumping module `\sky130_fd_sc_hd__o22a_4'.
Dumping module `\sky130_fd_sc_hd__o22ai_1'.
Dumping module `\sky130_fd_sc_hd__o22ai_2'.
Dumping module `\sky130_fd_sc_hd__o22ai_4'.
Dumping module `\sky130_fd_sc_hd__o2bb2a_1'.
Dumping module `\sky130_fd_sc_hd__o2bb2a_2'.
Dumping module `\sky130_fd_sc_hd__o2bb2a_4'.
Dumping module `\sky130_fd_sc_hd__o2bb2ai_1'.
Dumping module `\sky130_fd_sc_hd__o2bb2ai_2'.
Dumping module `\sky130_fd_sc_hd__o2bb2ai_4'.
Dumping module `\sky130_fd_sc_hd__o311a_1'.
Dumping module `\sky130_fd_sc_hd__o311a_2'.
Dumping module `\sky130_fd_sc_hd__o311a_4'.
Dumping module `\sky130_fd_sc_hd__o311ai_0'.
Dumping module `\sky130_fd_sc_hd__o311ai_1'.
Dumping module `\sky130_fd_sc_hd__o311ai_2'.
Dumping module `\sky130_fd_sc_hd__o311ai_4'.
Dumping module `\sky130_fd_sc_hd__o31a_1'.
Dumping module `\sky130_fd_sc_hd__o31a_2'.
Dumping module `\sky130_fd_sc_hd__o31a_4'.
Dumping module `\sky130_fd_sc_hd__o31ai_1'.
Dumping module `\sky130_fd_sc_hd__o31ai_2'.
Dumping module `\sky130_fd_sc_hd__o31ai_4'.
Dumping module `\sky130_fd_sc_hd__o32a_1'.
Dumping module `\sky130_fd_sc_hd__o32a_2'.
Dumping module `\sky130_fd_sc_hd__o32a_4'.
Dumping module `\sky130_fd_sc_hd__o32ai_1'.
Dumping module `\sky130_fd_sc_hd__o32ai_2'.
Dumping module `\sky130_fd_sc_hd__o32ai_4'.
Dumping module `\sky130_fd_sc_hd__o41a_1'.
Dumping module `\sky130_fd_sc_hd__o41a_2'.
Dumping module `\sky130_fd_sc_hd__o41a_4'.
Dumping module `\sky130_fd_sc_hd__o41ai_1'.
Dumping module `\sky130_fd_sc_hd__o41ai_2'.
Dumping module `\sky130_fd_sc_hd__o41ai_4'.
Dumping module `\sky130_fd_sc_hd__or2_0'.
Dumping module `\sky130_fd_sc_hd__or2_1'.
Dumping module `\sky130_fd_sc_hd__or2_2'.
Dumping module `\sky130_fd_sc_hd__or2_4'.
Dumping module `\sky130_fd_sc_hd__or2b_1'.
Dumping module `\sky130_fd_sc_hd__or2b_2'.
Dumping module `\sky130_fd_sc_hd__or2b_4'.
Dumping module `\sky130_fd_sc_hd__or3_1'.
Dumping module `\sky130_fd_sc_hd__or3_2'.
Dumping module `\sky130_fd_sc_hd__or3_4'.
Dumping module `\sky130_fd_sc_hd__or3b_1'.
Dumping module `\sky130_fd_sc_hd__or3b_2'.
Dumping module `\sky130_fd_sc_hd__or3b_4'.
Dumping module `\sky130_fd_sc_hd__or4_1'.
Dumping module `\sky130_fd_sc_hd__or4_2'.
Dumping module `\sky130_fd_sc_hd__or4_4'.
Dumping module `\sky130_fd_sc_hd__or4b_1'.
Dumping module `\sky130_fd_sc_hd__or4b_2'.
Dumping module `\sky130_fd_sc_hd__or4b_4'.
Dumping module `\sky130_fd_sc_hd__or4bb_1'.
Dumping module `\sky130_fd_sc_hd__or4bb_2'.
Dumping module `\sky130_fd_sc_hd__or4bb_4'.
Dumping module `\sky130_fd_sc_hd__probe_p_8'.
Dumping module `\sky130_fd_sc_hd__probec_p_8'.
Dumping module `\sky130_fd_sc_hd__sdfbbn_1'.
Dumping module `\sky130_fd_sc_hd__sdfbbn_2'.
Dumping module `\sky130_fd_sc_hd__sdfbbp_1'.
Dumping module `\sky130_fd_sc_hd__sdfrbp_1'.
Dumping module `\sky130_fd_sc_hd__sdfrbp_2'.
Dumping module `\sky130_fd_sc_hd__sdfrtn_1'.
Dumping module `\sky130_fd_sc_hd__sdfrtp_1'.
Dumping module `\sky130_fd_sc_hd__sdfrtp_2'.
Dumping module `\sky130_fd_sc_hd__sdfrtp_4'.
Dumping module `\sky130_fd_sc_hd__sdfsbp_1'.
Dumping module `\sky130_fd_sc_hd__sdfsbp_2'.
Dumping module `\sky130_fd_sc_hd__sdfstp_1'.
Dumping module `\sky130_fd_sc_hd__sdfstp_2'.
Dumping module `\sky130_fd_sc_hd__sdfstp_4'.
Dumping module `\sky130_fd_sc_hd__sdfxbp_1'.
Dumping module `\sky130_fd_sc_hd__sdfxbp_2'.
Dumping module `\sky130_fd_sc_hd__sdfxtp_1'.
Dumping module `\sky130_fd_sc_hd__sdfxtp_2'.
Dumping module `\sky130_fd_sc_hd__sdfxtp_4'.
Dumping module `\sky130_fd_sc_hd__sdlclkp_1'.
Dumping module `\sky130_fd_sc_hd__sdlclkp_2'.
Dumping module `\sky130_fd_sc_hd__sdlclkp_4'.
Dumping module `\sky130_fd_sc_hd__sedfxbp_1'.
Dumping module `\sky130_fd_sc_hd__sedfxbp_2'.
Dumping module `\sky130_fd_sc_hd__sedfxtp_1'.
Dumping module `\sky130_fd_sc_hd__sedfxtp_2'.
Dumping module `\sky130_fd_sc_hd__sedfxtp_4'.
Dumping module `\sky130_fd_sc_hd__xnor2_1'.
Dumping module `\sky130_fd_sc_hd__xnor2_2'.
Dumping module `\sky130_fd_sc_hd__xnor2_4'.
Dumping module `\sky130_fd_sc_hd__xnor3_1'.
Dumping module `\sky130_fd_sc_hd__xnor3_2'.
Dumping module `\sky130_fd_sc_hd__xnor3_4'.
Dumping module `\sky130_fd_sc_hd__xor2_1'.
Dumping module `\sky130_fd_sc_hd__xor2_2'.
Dumping module `\sky130_fd_sc_hd__xor2_4'.
Dumping module `\sky130_fd_sc_hd__xor3_1'.
Dumping module `\sky130_fd_sc_hd__xor3_2'.
Dumping module `\sky130_fd_sc_hd__xor3_4'.
End of script. Logfile hash: 4d38f4e6f2, CPU: user 0.12s system 0.03s, MEM: 56.83 MB peak
Yosys 0.62 (git sha1 7326bb7d6, g++ 13.3.0-6ubuntu2~24.04 -fPIC -O3)
Time spent: 53% 2x write_verilog (0 sec), 46% 2x read_liberty (0 sec), ...
yosys -p "read_verilog -D SYNTHESIS puf/puf_top.v puf/puf_bit.v puf/ro.v puf/arbiter.v puf/mux.v puf/counter.v ; read_verilog -lib sky130_blackboxes.v; hierarchy -top puf_top; proc; opt; techmap; opt; dfflibmap -liberty /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib; abc -liberty /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib; clean; stat; write_verilog -noattr puf/build/puf_top_synth.v"
/----------------------------------------------------------------------------\
| yosys -- Yosys Open SYnthesis Suite |
| Copyright (C) 2012 - 2026 Claire Xenia Wolf <claire@yosyshq.com> |
| Distributed under an ISC-like license, type "license" to see terms |
\----------------------------------------------------------------------------/
Yosys 0.62 (git sha1 7326bb7d6, g++ 13.3.0-6ubuntu2~24.04 -fPIC -O3)
-- Running command `read_verilog -D SYNTHESIS puf/puf_top.v puf/puf_bit.v puf/ro.v puf/arbiter.v puf/mux.v puf/counter.v ; read_verilog -lib sky130_blackboxes.v; hierarchy -top puf_top; proc; opt; techmap; opt; dfflibmap -liberty /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib; abc -liberty /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib; clean; stat; write_verilog -noattr puf/build/puf_top_synth.v' --
1. Executing Verilog-2005 frontend: puf/puf_top.v
Parsing Verilog input from `puf/puf_top.v' to AST representation.
Generating RTLIL representation for module `\puf_top'.
Successfully finished Verilog frontend.
2. Executing Verilog-2005 frontend: puf/puf_bit.v
Parsing Verilog input from `puf/puf_bit.v' to AST representation.
Generating RTLIL representation for module `\puf_bit'.
Successfully finished Verilog frontend.
3. Executing Verilog-2005 frontend: puf/ro.v
Parsing Verilog input from `puf/ro.v' to AST representation.
Generating RTLIL representation for module `\ro'.
Successfully finished Verilog frontend.
4. Executing Verilog-2005 frontend: puf/arbiter.v
Parsing Verilog input from `puf/arbiter.v' to AST representation.
Generating RTLIL representation for module `\arbiter'.
Successfully finished Verilog frontend.
5. Executing Verilog-2005 frontend: puf/mux.v
Parsing Verilog input from `puf/mux.v' to AST representation.
Generating RTLIL representation for module `\mux'.
Successfully finished Verilog frontend.
6. Executing Verilog-2005 frontend: puf/counter.v
Parsing Verilog input from `puf/counter.v' to AST representation.
Generating RTLIL representation for module `\counter'.
Successfully finished Verilog frontend.
7. Executing Verilog-2005 frontend: sky130_blackboxes.v
Parsing Verilog input from `sky130_blackboxes.v' to AST representation.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a2111o_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a2111o_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a2111o_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a2111oi_0'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a2111oi_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a2111oi_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a2111oi_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a211o_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a211o_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a211o_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a211oi_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a211oi_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a211oi_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a21bo_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a21bo_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a21bo_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a21boi_0'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a21boi_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a21boi_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a21boi_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a21o_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a21o_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a21o_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a21oi_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a21oi_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a21oi_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a221o_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a221o_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a221o_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a221oi_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a221oi_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a221oi_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a222oi_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a22o_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a22o_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a22o_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a22oi_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a22oi_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a22oi_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a2bb2o_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a2bb2o_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a2bb2o_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a2bb2oi_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a2bb2oi_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a2bb2oi_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a311o_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a311o_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a311o_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a311oi_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a311oi_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a311oi_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a31o_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a31o_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a31o_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a31oi_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a31oi_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a31oi_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a32o_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a32o_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a32o_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a32oi_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a32oi_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a32oi_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a41o_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a41o_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a41o_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a41oi_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a41oi_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__a41oi_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__and2_0'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__and2_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__and2_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__and2_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__and2b_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__and2b_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__and2b_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__and3_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__and3_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__and3_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__and3b_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__and3b_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__and3b_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__and4_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__and4_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__and4_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__and4b_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__and4b_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__and4b_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__and4bb_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__and4bb_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__and4bb_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__buf_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__buf_12'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__buf_16'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__buf_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__buf_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__buf_6'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__buf_8'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__bufbuf_16'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__bufbuf_8'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__bufinv_16'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__bufinv_8'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__clkbuf_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__clkbuf_16'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__clkbuf_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__clkbuf_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__clkbuf_8'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__clkdlybuf4s15_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__clkdlybuf4s15_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__clkdlybuf4s18_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__clkdlybuf4s18_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__clkdlybuf4s25_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__clkdlybuf4s25_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__clkdlybuf4s50_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__clkdlybuf4s50_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__clkinv_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__clkinv_16'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__clkinv_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__clkinv_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__clkinv_8'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__clkinvlp_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__clkinvlp_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__conb_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__decap_12'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__decap_3'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__decap_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__decap_6'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__decap_8'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__dfbbn_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__dfbbn_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__dfbbp_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__dfrbp_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__dfrbp_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__dfrtn_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__dfrtp_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__dfrtp_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__dfrtp_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__dfsbp_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__dfsbp_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__dfstp_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__dfstp_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__dfstp_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__dfxbp_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__dfxbp_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__dfxtp_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__dfxtp_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__dfxtp_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__diode_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__dlclkp_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__dlclkp_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__dlclkp_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__dlrbn_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__dlrbn_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__dlrbp_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__dlrbp_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__dlrtn_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__dlrtn_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__dlrtn_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__dlrtp_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__dlrtp_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__dlrtp_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__dlxbn_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__dlxbn_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__dlxbp_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__dlxtn_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__dlxtn_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__dlxtn_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__dlxtp_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__dlygate4sd1_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__dlygate4sd2_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__dlygate4sd3_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__dlymetal6s2s_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__dlymetal6s4s_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__dlymetal6s6s_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__ebufn_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__ebufn_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__ebufn_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__ebufn_8'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__edfxbp_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__edfxtp_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__einvn_0'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__einvn_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__einvn_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__einvn_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__einvn_8'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__einvp_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__einvp_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__einvp_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__einvp_8'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__fa_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__fa_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__fa_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__fah_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__fahcin_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__fahcon_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__ha_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__ha_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__ha_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__inv_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__inv_12'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__inv_16'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__inv_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__inv_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__inv_6'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__inv_8'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__lpflow_bleeder_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__lpflow_clkbufkapwr_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__lpflow_clkbufkapwr_16'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__lpflow_clkbufkapwr_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__lpflow_clkbufkapwr_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__lpflow_clkbufkapwr_8'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__lpflow_clkinvkapwr_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__lpflow_clkinvkapwr_16'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__lpflow_clkinvkapwr_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__lpflow_clkinvkapwr_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__lpflow_clkinvkapwr_8'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__lpflow_decapkapwr_12'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__lpflow_decapkapwr_3'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__lpflow_decapkapwr_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__lpflow_decapkapwr_6'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__lpflow_decapkapwr_8'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__lpflow_inputiso0n_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__lpflow_inputiso0p_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__lpflow_inputiso1n_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__lpflow_inputiso1p_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__lpflow_inputisolatch_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__lpflow_isobufsrc_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__lpflow_isobufsrc_16'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__lpflow_isobufsrc_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__lpflow_isobufsrc_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__lpflow_isobufsrc_8'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__lpflow_isobufsrckapwr_16'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__macro_sparecell'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__maj3_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__maj3_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__maj3_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__mux2_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__mux2_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__mux2_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__mux2_8'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__mux2i_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__mux2i_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__mux2i_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__mux4_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__mux4_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__mux4_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__nand2_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__nand2_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__nand2_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__nand2_8'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__nand2b_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__nand2b_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__nand2b_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__nand3_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__nand3_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__nand3_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__nand3b_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__nand3b_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__nand3b_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__nand4_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__nand4_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__nand4_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__nand4b_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__nand4b_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__nand4b_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__nand4bb_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__nand4bb_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__nand4bb_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__nor2_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__nor2_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__nor2_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__nor2_8'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__nor2b_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__nor2b_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__nor2b_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__nor3_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__nor3_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__nor3_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__nor3b_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__nor3b_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__nor3b_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__nor4_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__nor4_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__nor4_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__nor4b_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__nor4b_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__nor4b_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__nor4bb_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__nor4bb_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__nor4bb_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o2111a_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o2111a_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o2111a_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o2111ai_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o2111ai_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o2111ai_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o211a_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o211a_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o211a_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o211ai_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o211ai_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o211ai_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o21a_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o21a_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o21a_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o21ai_0'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o21ai_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o21ai_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o21ai_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o21ba_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o21ba_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o21ba_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o21bai_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o21bai_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o21bai_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o221a_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o221a_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o221a_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o221ai_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o221ai_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o221ai_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o22a_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o22a_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o22a_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o22ai_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o22ai_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o22ai_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o2bb2a_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o2bb2a_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o2bb2a_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o2bb2ai_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o2bb2ai_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o2bb2ai_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o311a_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o311a_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o311a_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o311ai_0'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o311ai_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o311ai_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o311ai_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o31a_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o31a_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o31a_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o31ai_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o31ai_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o31ai_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o32a_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o32a_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o32a_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o32ai_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o32ai_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o32ai_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o41a_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o41a_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o41a_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o41ai_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o41ai_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__o41ai_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__or2_0'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__or2_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__or2_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__or2_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__or2b_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__or2b_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__or2b_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__or3_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__or3_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__or3_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__or3b_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__or3b_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__or3b_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__or4_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__or4_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__or4_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__or4b_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__or4b_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__or4b_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__or4bb_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__or4bb_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__or4bb_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__probe_p_8'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__probec_p_8'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__sdfbbn_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__sdfbbn_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__sdfbbp_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__sdfrbp_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__sdfrbp_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__sdfrtn_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__sdfrtp_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__sdfrtp_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__sdfrtp_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__sdfsbp_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__sdfsbp_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__sdfstp_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__sdfstp_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__sdfstp_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__sdfxbp_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__sdfxbp_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__sdfxtp_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__sdfxtp_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__sdfxtp_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__sdlclkp_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__sdlclkp_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__sdlclkp_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__sedfxbp_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__sedfxbp_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__sedfxtp_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__sedfxtp_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__sedfxtp_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__xnor2_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__xnor2_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__xnor2_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__xnor3_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__xnor3_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__xnor3_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__xor2_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__xor2_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__xor2_4'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__xor3_1'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__xor3_2'.
Generating RTLIL representation for module `\sky130_fd_sc_hd__xor3_4'.
Successfully finished Verilog frontend.
8. Executing HIERARCHY pass (managing design hierarchy).
8.1. Analyzing design hierarchy..
Top module: \puf_top
Used module: \puf_bit
Used module: \ro
Used module: \arbiter
Used module: \counter
Used module: \mux
Parameter \THRESHOLD = 16'1111111111111111
8.2. Executing AST frontend in derive mode using pre-parsed AST for module `\counter'.
Parameter \THRESHOLD = 16'1111111111111111
Generating RTLIL representation for module `$paramod\counter\THRESHOLD=16'1111111111111111'.
Parameter \THRESHOLD = 16'1111111111111111
Found cached RTLIL representation for module `$paramod\counter\THRESHOLD=16'1111111111111111'.
8.3. Analyzing design hierarchy..
Top module: \puf_top
Used module: \puf_bit
Used module: \ro
Used module: \arbiter
Used module: $paramod\counter\THRESHOLD=16'1111111111111111
Used module: \mux
8.4. Analyzing design hierarchy..
Top module: \puf_top
Used module: \puf_bit
Used module: \ro
Used module: \arbiter
Used module: $paramod\counter\THRESHOLD=16'1111111111111111
Used module: \mux
Removing unused module `\counter'.
Removed 1 unused modules.
9. Executing PROC pass (convert processes to netlists).
9.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
9.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$puf/counter.v:11$16 in module $paramod\counter\THRESHOLD=16'1111111111111111.
Marked 4 switch rules as full_case in process $proc$puf/arbiter.v:28$3 in module arbiter.
Marked 1 switch rules as full_case in process $proc$puf/arbiter.v:19$1 in module arbiter.
Removed a total of 0 dead cases.
9.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 3 assignments to connections.
9.4. Executing PROC_INIT pass (extract init attributes).
9.5. Executing PROC_ARST pass (detect async resets in processes).
Found async reset \rst_n in `$paramod\counter\THRESHOLD=16'1111111111111111.$proc$puf/counter.v:11$16'.
Found async reset \rst_n in `\arbiter.$proc$puf/arbiter.v:19$1'.
9.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~5 debug messages>
9.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod\counter\THRESHOLD=16'1111111111111111.$proc$puf/counter.v:11$16'.
1/1: $0\data_cnt[15:0]
Creating decoders for process `\arbiter.$proc$puf/arbiter.v:28$3'.
1/12: $4\next_state[1:0]
2/12: $4\data_out[0:0]
3/12: $4\finish[0:0]
4/12: $3\next_state[1:0]
5/12: $3\data_out[0:0]
6/12: $3\finish[0:0]
7/12: $2\next_state[1:0]
8/12: $2\data_out[0:0]
9/12: $2\finish[0:0]
10/12: $1\next_state[1:0]
11/12: $1\data_out[0:0]
12/12: $1\finish[0:0]
Creating decoders for process `\arbiter.$proc$puf/arbiter.v:19$1'.
1/1: $0\state[1:0]
9.8. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `\arbiter.\finish' from process `\arbiter.$proc$puf/arbiter.v:28$3'.
No latch inferred for signal `\arbiter.\data_out' from process `\arbiter.$proc$puf/arbiter.v:28$3'.
No latch inferred for signal `\arbiter.\next_state' from process `\arbiter.$proc$puf/arbiter.v:28$3'.
9.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod\counter\THRESHOLD=16'1111111111111111.\data_cnt' using process `$paramod\counter\THRESHOLD=16'1111111111111111.$proc$puf/counter.v:11$16'.
created $adff cell `$procdff$140' with positive edge clock and positive level reset.
Creating register for signal `\arbiter.\state' using process `\arbiter.$proc$puf/arbiter.v:19$1'.
created $adff cell `$procdff$145' with positive edge clock and positive level reset.
9.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
9.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod\counter\THRESHOLD=16'1111111111111111.$proc$puf/counter.v:11$16'.
Removing empty process `$paramod\counter\THRESHOLD=16'1111111111111111.$proc$puf/counter.v:11$16'.
Found and cleaned up 4 empty switches in `\arbiter.$proc$puf/arbiter.v:28$3'.
Removing empty process `arbiter.$proc$puf/arbiter.v:28$3'.
Removing empty process `arbiter.$proc$puf/arbiter.v:19$1'.
Cleaned up 5 empty switches.
9.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod\counter\THRESHOLD=16'1111111111111111.
<suppressed ~2 debug messages>
Optimizing module mux.
Optimizing module arbiter.
<suppressed ~18 debug messages>
Optimizing module ro.
Optimizing module puf_bit.
Optimizing module puf_top.
10. Executing OPT pass (performing simple optimizations).
10.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod\counter\THRESHOLD=16'1111111111111111.
Optimizing module mux.
Optimizing module arbiter.
Optimizing module ro.
Optimizing module puf_bit.
Optimizing module puf_top.
10.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod\counter\THRESHOLD=16'1111111111111111'.
Computing hashes of 8 cells of `$paramod\counter\THRESHOLD=16'1111111111111111'.
Finding duplicate cells in `$paramod\counter\THRESHOLD=16'1111111111111111'.
Finding identical cells in module `\mux'.
Computing hashes of 1 cells of `\mux'.
Finding duplicate cells in `\mux'.
Finding identical cells in module `\arbiter'.
Computing hashes of 49 cells of `\arbiter'.
Finding duplicate cells in `\arbiter'.
Computing hashes of 35 cells of `\arbiter'.
Finding duplicate cells in `\arbiter'.
<suppressed ~42 debug messages>
Finding identical cells in module `\ro'.
Computing hashes of 8 cells of `\ro'.
Finding duplicate cells in `\ro'.
Finding identical cells in module `\puf_bit'.
Computing hashes of 37 cells of `\puf_bit'.
Finding duplicate cells in `\puf_bit'.
Finding identical cells in module `\puf_top'.
Computing hashes of 8 cells of `\puf_top'.
Finding duplicate cells in `\puf_top'.
Removed a total of 14 cells.
10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module $paramod\counter\THRESHOLD=16'1111111111111111..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \mux..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \arbiter..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
dead port 2/2 on $mux $procmux$103.
dead port 2/2 on $mux $procmux$95.
dead port 1/2 on $mux $procmux$93.
dead port 2/2 on $mux $procmux$84.
dead port 1/2 on $mux $procmux$82.
dead port 2/2 on $mux $procmux$73.
dead port 1/2 on $mux $procmux$71.
dead port 2/2 on $mux $procmux$62.
dead port 2/2 on $mux $procmux$119.
dead port 1/2 on $mux $procmux$60.
dead port 1/2 on $mux $procmux$57.
dead port 2/2 on $mux $procmux$49.
dead port 1/2 on $mux $procmux$47.
dead port 1/2 on $mux $procmux$44.
dead port 2/2 on $mux $procmux$36.
dead port 1/2 on $mux $procmux$34.
dead port 1/2 on $mux $procmux$31.
dead port 2/2 on $mux $procmux$111.
Running muxtree optimizer on module \ro..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \puf_bit..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \puf_top..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 18 multiplexer ports.
<suppressed ~33 debug messages>
10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module $paramod\counter\THRESHOLD=16'1111111111111111.
Optimizing cells in module \mux.
Optimizing cells in module \arbiter.
New ctrl vector for $pmux cell $procmux$122: { $procmux$130_CMP $auto$opt_reduce.cc:137:opt_pmux$147 }
New ctrl vector for $pmux cell $procmux$132: { $procmux$130_CMP $auto$opt_reduce.cc:137:opt_pmux$149 }
New ctrl vector for $pmux cell $procmux$128: $procmux$129_CMP
New ctrl vector for $pmux cell $procmux$132: $auto$opt_reduce.cc:137:opt_pmux$149
Optimizing cells in module \arbiter.
Optimizing cells in module \ro.
Optimizing cells in module \puf_bit.
Optimizing cells in module \puf_top.
Performed a total of 8 changes.
10.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod\counter\THRESHOLD=16'1111111111111111'.
Computing hashes of 8 cells of `$paramod\counter\THRESHOLD=16'1111111111111111'.
Finding duplicate cells in `$paramod\counter\THRESHOLD=16'1111111111111111'.
Finding identical cells in module `\mux'.
Computing hashes of 1 cells of `\mux'.
Finding duplicate cells in `\mux'.
Finding identical cells in module `\arbiter'.
Computing hashes of 15 cells of `\arbiter'.
Finding duplicate cells in `\arbiter'.
Computing hashes of 14 cells of `\arbiter'.
Finding duplicate cells in `\arbiter'.
<suppressed ~3 debug messages>
Finding identical cells in module `\ro'.
Computing hashes of 8 cells of `\ro'.
Finding duplicate cells in `\ro'.
Finding identical cells in module `\puf_bit'.
Computing hashes of 37 cells of `\puf_bit'.
Finding duplicate cells in `\puf_bit'.
Finding identical cells in module `\puf_top'.
Computing hashes of 8 cells of `\puf_top'.
Finding duplicate cells in `\puf_top'.
Removed a total of 1 cells.
10.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding EN signal on $procdff$140 ($adff) from module $paramod\counter\THRESHOLD=16'1111111111111111 (D = $add$puf/counter.v:16$20_Y [15:0], Q = \data_cnt).
Adding EN signal on $procdff$145 ($adff) from module arbiter (D = $procmux$122_Y, Q = \state).
10.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module $paramod\counter\THRESHOLD=16'1111111111111111..
Finding unused cells or wires in module \mux..
Finding unused cells or wires in module \arbiter..
Finding unused cells or wires in module \ro..
Finding unused cells or wires in module \puf_bit..
Finding unused cells or wires in module \puf_top..
Removed 6 unused cells and 87 unused wires.
<suppressed ~9 debug messages>
10.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod\counter\THRESHOLD=16'1111111111111111.
Optimizing module arbiter.
<suppressed ~2 debug messages>
Optimizing module mux.
Optimizing module puf_bit.
Optimizing module puf_top.
Optimizing module ro.
10.9. Rerunning OPT passes. (Maybe there is more to do..)
10.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module $paramod\counter\THRESHOLD=16'1111111111111111..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \arbiter..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \mux..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \puf_bit..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \puf_top..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \ro..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
<suppressed ~9 debug messages>
10.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module $paramod\counter\THRESHOLD=16'1111111111111111.
Optimizing cells in module \arbiter.
Optimizing cells in module \mux.
Optimizing cells in module \puf_bit.
Optimizing cells in module \puf_top.
Optimizing cells in module \ro.
Performed a total of 0 changes.
10.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod\counter\THRESHOLD=16'1111111111111111'.
Computing hashes of 5 cells of `$paramod\counter\THRESHOLD=16'1111111111111111'.
Finding duplicate cells in `$paramod\counter\THRESHOLD=16'1111111111111111'.
Finding identical cells in module `\arbiter'.
Computing hashes of 13 cells of `\arbiter'.
Finding duplicate cells in `\arbiter'.
Finding identical cells in module `\mux'.
Computing hashes of 1 cells of `\mux'.
Finding duplicate cells in `\mux'.
Finding identical cells in module `\puf_bit'.
Computing hashes of 37 cells of `\puf_bit'.
Finding duplicate cells in `\puf_bit'.
Finding identical cells in module `\puf_top'.
Computing hashes of 8 cells of `\puf_top'.
Finding duplicate cells in `\puf_top'.
Finding identical cells in module `\ro'.
Computing hashes of 7 cells of `\ro'.
Finding duplicate cells in `\ro'.
Removed a total of 0 cells.
10.13. Executing OPT_DFF pass (perform DFF optimizations).
10.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module $paramod\counter\THRESHOLD=16'1111111111111111..
Finding unused cells or wires in module \arbiter..
Finding unused cells or wires in module \mux..
Finding unused cells or wires in module \puf_bit..
Finding unused cells or wires in module \puf_top..
Finding unused cells or wires in module \ro..
Removed 1 unused cells and 1 unused wires.
<suppressed ~2 debug messages>
10.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod\counter\THRESHOLD=16'1111111111111111.
Optimizing module arbiter.
Optimizing module mux.
Optimizing module puf_bit.
Optimizing module puf_top.
Optimizing module ro.
10.16. Rerunning OPT passes. (Maybe there is more to do..)
10.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module $paramod\counter\THRESHOLD=16'1111111111111111..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \arbiter..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \mux..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \puf_bit..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \puf_top..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \ro..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
<suppressed ~9 debug messages>
10.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module $paramod\counter\THRESHOLD=16'1111111111111111.
Optimizing cells in module \arbiter.
Optimizing cells in module \mux.
Optimizing cells in module \puf_bit.
Optimizing cells in module \puf_top.
Optimizing cells in module \ro.
Performed a total of 0 changes.
10.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod\counter\THRESHOLD=16'1111111111111111'.
Computing hashes of 5 cells of `$paramod\counter\THRESHOLD=16'1111111111111111'.
Finding duplicate cells in `$paramod\counter\THRESHOLD=16'1111111111111111'.
Finding identical cells in module `\arbiter'.
Computing hashes of 12 cells of `\arbiter'.
Finding duplicate cells in `\arbiter'.
Finding identical cells in module `\mux'.
Computing hashes of 1 cells of `\mux'.
Finding duplicate cells in `\mux'.
Finding identical cells in module `\puf_bit'.
Computing hashes of 37 cells of `\puf_bit'.
Finding duplicate cells in `\puf_bit'.
Finding identical cells in module `\puf_top'.
Computing hashes of 8 cells of `\puf_top'.
Finding duplicate cells in `\puf_top'.
Finding identical cells in module `\ro'.
Computing hashes of 7 cells of `\ro'.
Finding duplicate cells in `\ro'.
Removed a total of 0 cells.
10.20. Executing OPT_DFF pass (perform DFF optimizations).
10.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module $paramod\counter\THRESHOLD=16'1111111111111111..
Finding unused cells or wires in module \arbiter..
Finding unused cells or wires in module \mux..
Finding unused cells or wires in module \puf_bit..
Finding unused cells or wires in module \puf_top..
Finding unused cells or wires in module \ro..
10.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod\counter\THRESHOLD=16'1111111111111111.
Optimizing module arbiter.
Optimizing module mux.
Optimizing module puf_bit.
Optimizing module puf_top.
Optimizing module ro.
10.23. Finished fast OPT passes. (There is nothing left to do.)
11. Executing TECHMAP pass (map to technology primitives).
11.1. Executing Verilog-2005 frontend: /foss/tools/yosys/bin/../share/yosys/techmap.v
Parsing Verilog input from `/foss/tools/yosys/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `$__div_mod_u'.
Generating RTLIL representation for module `$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Generating RTLIL representation for module `$connect'.
Generating RTLIL representation for module `$input_port'.
Successfully finished Verilog frontend.
11.2. Continuing TECHMAP pass.
Using template $paramod$constmap:446553370afc6c2aa6cc0b8f657b7f64b237ff7c$paramod$962bb79c2a50a422516483c1c9c06046761917ac\_90_shift_shiftx for cells of type $shiftx.
Using extmapper simplemap for cells of type $mux.
Using extmapper simplemap for cells of type $adffe.
Using extmapper simplemap for cells of type $reduce_or.
Using extmapper simplemap for cells of type $logic_and.
Using template $paramod$521ce43182eecb9f60c72393a788160d2c356bf5\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $eq.
Using extmapper simplemap for cells of type $logic_not.
Using extmapper simplemap for cells of type $and.
Running "alumacc" on wrapper $extern:wrap:$lt:A_SIGNED=0:A_WIDTH=16:B_SIGNED=0:B_WIDTH=16:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$lt:A_SIGNED=0:A_WIDTH=16:B_SIGNED=0:B_WIDTH=16:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$lt:A_SIGNED=0:A_WIDTH=16:B_SIGNED=0:B_WIDTH=16:Y_WIDTH=1:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=16:B_SIGNED=0:B_WIDTH=32:Y_WIDTH=32:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=16:B_SIGNED=0:B_WIDTH=32:Y_WIDTH=32:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=16:B_SIGNED=0:B_WIDTH=32:Y_WIDTH=32:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $paramod$6df0329addda9228fcc2546de2aaf14ad26c98e1\_90_alu for cells of type $alu.
Using extmapper simplemap for cells of type $not.
Using template $paramod$2bd81f420048247ff6903399c560fe0f8bd48ccc\_90_alu for cells of type $alu.
Using extmapper simplemap for cells of type $xor.
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000010000 for cells of type $fa.
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000010000 for cells of type $lcu.
Using extmapper simplemap for cells of type $pos.
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000100000 for cells of type $fa.
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000100000 for cells of type $lcu.
Using extmapper simplemap for cells of type $or.
No more expansions possible.
<suppressed ~910 debug messages>
12. Executing OPT pass (performing simple optimizations).
12.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod\counter\THRESHOLD=16'1111111111111111.
<suppressed ~527 debug messages>
Optimizing module arbiter.
<suppressed ~13 debug messages>
Optimizing module mux.
Optimizing module puf_bit.
Optimizing module puf_top.
Optimizing module ro.
12.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod\counter\THRESHOLD=16'1111111111111111'.
Computing hashes of 134 cells of `$paramod\counter\THRESHOLD=16'1111111111111111'.
Finding duplicate cells in `$paramod\counter\THRESHOLD=16'1111111111111111'.
Computing hashes of 123 cells of `$paramod\counter\THRESHOLD=16'1111111111111111'.
Finding duplicate cells in `$paramod\counter\THRESHOLD=16'1111111111111111'.
Computing hashes of 117 cells of `$paramod\counter\THRESHOLD=16'1111111111111111'.
Finding duplicate cells in `$paramod\counter\THRESHOLD=16'1111111111111111'.
Computing hashes of 111 cells of `$paramod\counter\THRESHOLD=16'1111111111111111'.
Finding duplicate cells in `$paramod\counter\THRESHOLD=16'1111111111111111'.
Computing hashes of 103 cells of `$paramod\counter\THRESHOLD=16'1111111111111111'.
Finding duplicate cells in `$paramod\counter\THRESHOLD=16'1111111111111111'.
Computing hashes of 96 cells of `$paramod\counter\THRESHOLD=16'1111111111111111'.
Finding duplicate cells in `$paramod\counter\THRESHOLD=16'1111111111111111'.
Computing hashes of 92 cells of `$paramod\counter\THRESHOLD=16'1111111111111111'.
Finding duplicate cells in `$paramod\counter\THRESHOLD=16'1111111111111111'.
Computing hashes of 91 cells of `$paramod\counter\THRESHOLD=16'1111111111111111'.
Finding duplicate cells in `$paramod\counter\THRESHOLD=16'1111111111111111'.
<suppressed ~129 debug messages>
Finding identical cells in module `\arbiter'.
Computing hashes of 21 cells of `\arbiter'.
Finding duplicate cells in `\arbiter'.
Computing hashes of 20 cells of `\arbiter'.
Finding duplicate cells in `\arbiter'.
<suppressed ~3 debug messages>
Finding identical cells in module `\mux'.
Computing hashes of 64 cells of `\mux'.
Finding duplicate cells in `\mux'.
Finding identical cells in module `\puf_bit'.
Computing hashes of 37 cells of `\puf_bit'.
Finding duplicate cells in `\puf_bit'.
Finding identical cells in module `\puf_top'.
Computing hashes of 8 cells of `\puf_top'.
Finding duplicate cells in `\puf_top'.
Finding identical cells in module `\ro'.
Computing hashes of 7 cells of `\ro'.
Finding duplicate cells in `\ro'.
Removed a total of 44 cells.
12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module $paramod\counter\THRESHOLD=16'1111111111111111..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \arbiter..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \mux..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \puf_bit..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \puf_top..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \ro..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module $paramod\counter\THRESHOLD=16'1111111111111111.
Optimizing cells in module \arbiter.
Optimizing cells in module \mux.
Optimizing cells in module \puf_bit.
Optimizing cells in module \puf_top.
Optimizing cells in module \ro.
Performed a total of 0 changes.
12.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod\counter\THRESHOLD=16'1111111111111111'.
Computing hashes of 91 cells of `$paramod\counter\THRESHOLD=16'1111111111111111'.
Finding duplicate cells in `$paramod\counter\THRESHOLD=16'1111111111111111'.
Finding identical cells in module `\arbiter'.
Computing hashes of 20 cells of `\arbiter'.
Finding duplicate cells in `\arbiter'.
Finding identical cells in module `\mux'.
Computing hashes of 64 cells of `\mux'.
Finding duplicate cells in `\mux'.
Finding identical cells in module `\puf_bit'.
Computing hashes of 37 cells of `\puf_bit'.
Finding duplicate cells in `\puf_bit'.
Finding identical cells in module `\puf_top'.
Computing hashes of 8 cells of `\puf_top'.
Finding duplicate cells in `\puf_top'.
Finding identical cells in module `\ro'.
Computing hashes of 7 cells of `\ro'.
Finding duplicate cells in `\ro'.
Removed a total of 0 cells.
12.6. Executing OPT_DFF pass (perform DFF optimizations).
12.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module $paramod\counter\THRESHOLD=16'1111111111111111..
Finding unused cells or wires in module \arbiter..
Finding unused cells or wires in module \mux..
Finding unused cells or wires in module \puf_bit..
Finding unused cells or wires in module \puf_top..
Finding unused cells or wires in module \ro..
Removed 49 unused cells and 270 unused wires.
<suppressed ~52 debug messages>
12.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod\counter\THRESHOLD=16'1111111111111111.
Optimizing module arbiter.
Optimizing module mux.
Optimizing module puf_bit.
Optimizing module puf_top.
Optimizing module ro.
12.9. Rerunning OPT passes. (Maybe there is more to do..)
12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module $paramod\counter\THRESHOLD=16'1111111111111111..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \arbiter..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \mux..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \puf_bit..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \puf_top..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \ro..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module $paramod\counter\THRESHOLD=16'1111111111111111.
Optimizing cells in module \arbiter.
Optimizing cells in module \mux.
Optimizing cells in module \puf_bit.
Optimizing cells in module \puf_top.
Optimizing cells in module \ro.
Performed a total of 0 changes.
12.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod\counter\THRESHOLD=16'1111111111111111'.
Computing hashes of 91 cells of `$paramod\counter\THRESHOLD=16'1111111111111111'.
Finding duplicate cells in `$paramod\counter\THRESHOLD=16'1111111111111111'.
Finding identical cells in module `\arbiter'.
Computing hashes of 20 cells of `\arbiter'.
Finding duplicate cells in `\arbiter'.
Finding identical cells in module `\mux'.
Computing hashes of 15 cells of `\mux'.
Finding duplicate cells in `\mux'.
Finding identical cells in module `\puf_bit'.
Computing hashes of 37 cells of `\puf_bit'.
Finding duplicate cells in `\puf_bit'.
Finding identical cells in module `\puf_top'.
Computing hashes of 8 cells of `\puf_top'.
Finding duplicate cells in `\puf_top'.
Finding identical cells in module `\ro'.
Computing hashes of 7 cells of `\ro'.
Finding duplicate cells in `\ro'.
Removed a total of 0 cells.
12.13. Executing OPT_DFF pass (perform DFF optimizations).
12.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module $paramod\counter\THRESHOLD=16'1111111111111111..
Finding unused cells or wires in module \arbiter..
Finding unused cells or wires in module \mux..
Finding unused cells or wires in module \puf_bit..
Finding unused cells or wires in module \puf_top..
Finding unused cells or wires in module \ro..
12.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod\counter\THRESHOLD=16'1111111111111111.
Optimizing module arbiter.
Optimizing module mux.
Optimizing module puf_bit.
Optimizing module puf_top.
Optimizing module ro.
12.16. Finished fast OPT passes. (There is nothing left to do.)
13. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).
cell sky130_fd_sc_hd__dfxtp_1 (noninv, pins=3, area=20.02) is a direct match for cell type $_DFF_P_.
cell sky130_fd_sc_hd__dfrtn_1 (noninv, pins=4, area=25.02) is a direct match for cell type $_DFF_NN0_.
cell sky130_fd_sc_hd__dfrtp_1 (noninv, pins=4, area=25.02) is a direct match for cell type $_DFF_PN0_.
cell sky130_fd_sc_hd__dfstp_2 (noninv, pins=4, area=26.28) is a direct match for cell type $_DFF_PN1_.
cell sky130_fd_sc_hd__edfxtp_1 (noninv, pins=4, area=30.03) is a direct match for cell type $_DFFE_PP_.
cell sky130_fd_sc_hd__dfbbn_1 (noninv, pins=6, area=32.53) is a direct match for cell type $_DFFSR_NNN_.
cell sky130_fd_sc_hd__dfbbp_1 (noninv, pins=6, area=32.53) is a direct match for cell type $_DFFSR_PNN_.
final dff cell mappings:
unmapped dff cell: $_DFF_N_
\sky130_fd_sc_hd__dfxtp_1 _DFF_P_ (.CLK( C), .D( D), .Q( Q));
\sky130_fd_sc_hd__dfrtn_1 _DFF_NN0_ (.CLK_N( C), .D( D), .Q( Q), .RESET_B( R));
unmapped dff cell: $_DFF_NN1_
unmapped dff cell: $_DFF_NP0_
unmapped dff cell: $_DFF_NP1_
\sky130_fd_sc_hd__dfrtp_1 _DFF_PN0_ (.CLK( C), .D( D), .Q( Q), .RESET_B( R));
\sky130_fd_sc_hd__dfstp_2 _DFF_PN1_ (.CLK( C), .D( D), .Q( Q), .SET_B( R));
unmapped dff cell: $_DFF_PP0_
unmapped dff cell: $_DFF_PP1_
unmapped dff cell: $_DFFE_NN_
unmapped dff cell: $_DFFE_NP_
unmapped dff cell: $_DFFE_PN_
\sky130_fd_sc_hd__edfxtp_1 _DFFE_PP_ (.CLK( C), .D( D), .DE( E), .Q( Q));
\sky130_fd_sc_hd__dfbbn_1 _DFFSR_NNN_ (.CLK_N( C), .D( D), .Q( Q), .Q_N(~Q), .RESET_B( R), .SET_B( S));
unmapped dff cell: $_DFFSR_NNP_
unmapped dff cell: $_DFFSR_NPN_
unmapped dff cell: $_DFFSR_NPP_
\sky130_fd_sc_hd__dfbbp_1 _DFFSR_PNN_ (.CLK( C), .D( D), .Q( Q), .Q_N(~Q), .RESET_B( R), .SET_B( S));
unmapped dff cell: $_DFFSR_PNP_
unmapped dff cell: $_DFFSR_PPN_
unmapped dff cell: $_DFFSR_PPP_
13.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
<suppressed ~24 debug messages>
Mapping DFF cells in module `$paramod\counter\THRESHOLD=16'1111111111111111':
mapped 16 $_DFF_PN0_ cells to \sky130_fd_sc_hd__dfrtp_1 cells.
Mapping DFF cells in module `\arbiter':
mapped 2 $_DFF_PN0_ cells to \sky130_fd_sc_hd__dfrtp_1 cells.
Mapping DFF cells in module `\mux':
Mapping DFF cells in module `\puf_bit':
Mapping DFF cells in module `\puf_top':
Mapping DFF cells in module `\ro':
14. Executing ABC pass (technology mapping using ABC).
14.1. Extracting gate netlist of module `$paramod\counter\THRESHOLD=16'1111111111111111' to `<abc-temp-dir>/input.blif'..
14.1.1. Executed ABC.
Extracted 91 gates and 108 wires to a netlist network with 17 inputs and 17 outputs.
Running ABC script: <abc-temp-dir>/abc.script
ABC: UC Berkeley, ABC 1.01 (compiled Feb 14 2026 00:59:35)
ABC: abc 01> empty
ABC: abc 01> source <abc-temp-dir>/abc.script
ABC: + read_blif <abc-temp-dir>/input.blif
ABC: + read_lib -w /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
ABC: Parsing finished successfully. Parsing time = 0.08 sec
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__decap_12" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__decap_3" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__decap_4" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__decap_6" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__decap_8" without logic function.
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfbbn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfbbn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfbbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfsbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfsbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_4".
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__diode_2" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__dlclkp_1" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__dlclkp_2" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__dlclkp_4" without logic function.
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrbn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrbn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrtn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrtn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrtn_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrtp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrtp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrtp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxbn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxbn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtp_1".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_1".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_2".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_4".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_8".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__edfxbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__edfxtp_1".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvn_0".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvn_1".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvn_2".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvn_4".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvn_8".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvp_1".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvp_2".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvp_4".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvp_8".
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__lpflow_bleeder_1" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__lpflow_decapkapwr_12" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__lpflow_decapkapwr_3" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__lpflow_decapkapwr_4" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__lpflow_decapkapwr_6" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__lpflow_decapkapwr_8" without logic function.
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__lpflow_inputisolatch_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfbbn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfbbn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfbbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfrbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfrbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfrtn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfrtp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfrtp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfrtp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfsbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfsbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfstp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfstp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfstp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfxbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfxbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfxtp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfxtp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfxtp_4".
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__sdlclkp_1" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__sdlclkp_2" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__sdlclkp_4" without logic function.
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sedfxbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sedfxbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sedfxtp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sedfxtp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sedfxtp_4".
ABC: Library "sky130_fd_sc_hd__tt_025C_1v80" from "/foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib" has 334 cells (94 skipped: 63 seq; 13 tri-state; 18 no func; 0 dont_use; 0 with 2 outputs; 0 with 3+ outputs). Time = 0.11 sec
ABC: Memory = 19.85 MB. Time = 0.11 sec
ABC: Warning: Detected 9 multi-output cells (for example, "sky130_fd_sc_hd__fa_1").
ABC: + strash
ABC: + &get -n
ABC: + &fraig -x
ABC: + &put
ABC: + scorr
ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
ABC: + dc2
ABC: + dretime
ABC: + strash
ABC: + &get -n
ABC: + &dch -f
ABC: + &nf
ABC: + &put
ABC: + write_blif <abc-temp-dir>/output.blif
ABC:
ABC: YOSYS_ABC_DONE
14.1.2. Re-integrating ABC results.
ABC RESULTS: sky130_fd_sc_hd__a21oi_1 cells: 2
ABC RESULTS: sky130_fd_sc_hd__a31o_1 cells: 1
ABC RESULTS: sky130_fd_sc_hd__a31oi_1 cells: 2
ABC RESULTS: sky130_fd_sc_hd__and2_0 cells: 1
ABC RESULTS: sky130_fd_sc_hd__and3_1 cells: 1
ABC RESULTS: sky130_fd_sc_hd__and4_1 cells: 2
ABC RESULTS: sky130_fd_sc_hd__and4b_1 cells: 1
ABC RESULTS: sky130_fd_sc_hd__nand2_1 cells: 5
ABC RESULTS: sky130_fd_sc_hd__nand3_1 cells: 4
ABC RESULTS: sky130_fd_sc_hd__nand4_1 cells: 3
ABC RESULTS: sky130_fd_sc_hd__nor2_1 cells: 2
ABC RESULTS: sky130_fd_sc_hd__nor2b_1 cells: 3
ABC RESULTS: sky130_fd_sc_hd__nor3_1 cells: 1
ABC RESULTS: sky130_fd_sc_hd__o2111a_1 cells: 1
ABC RESULTS: sky130_fd_sc_hd__o31a_1 cells: 1
ABC RESULTS: sky130_fd_sc_hd__xnor2_1 cells: 9
ABC RESULTS: sky130_fd_sc_hd__xor2_1 cells: 2
ABC RESULTS: internal signals: 74
ABC RESULTS: input signals: 17
ABC RESULTS: output signals: 17
Removing temp directory.
14.2. Extracting gate netlist of module `\arbiter' to `<abc-temp-dir>/input.blif'..
14.2.1. Executed ABC.
Extracted 20 gates and 26 wires to a netlist network with 4 inputs and 4 outputs.
Running ABC script: <abc-temp-dir>/abc.script
ABC: UC Berkeley, ABC 1.01 (compiled Feb 14 2026 00:59:35)
ABC: abc 01> empty
ABC: abc 01> source <abc-temp-dir>/abc.script
ABC: + read_blif <abc-temp-dir>/input.blif
ABC: + read_lib -w /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
ABC: Parsing finished successfully. Parsing time = 0.08 sec
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__decap_12" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__decap_3" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__decap_4" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__decap_6" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__decap_8" without logic function.
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfbbn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfbbn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfbbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfsbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfsbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_4".
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__diode_2" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__dlclkp_1" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__dlclkp_2" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__dlclkp_4" without logic function.
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrbn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrbn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrtn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrtn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrtn_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrtp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrtp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrtp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxbn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxbn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtp_1".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_1".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_2".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_4".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_8".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__edfxbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__edfxtp_1".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvn_0".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvn_1".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvn_2".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvn_4".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvn_8".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvp_1".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvp_2".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvp_4".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvp_8".
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__lpflow_bleeder_1" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__lpflow_decapkapwr_12" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__lpflow_decapkapwr_3" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__lpflow_decapkapwr_4" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__lpflow_decapkapwr_6" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__lpflow_decapkapwr_8" without logic function.
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__lpflow_inputisolatch_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfbbn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfbbn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfbbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfrbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfrbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfrtn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfrtp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfrtp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfrtp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfsbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfsbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfstp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfstp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfstp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfxbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfxbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfxtp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfxtp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfxtp_4".
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__sdlclkp_1" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__sdlclkp_2" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__sdlclkp_4" without logic function.
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sedfxbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sedfxbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sedfxtp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sedfxtp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sedfxtp_4".
ABC: Library "sky130_fd_sc_hd__tt_025C_1v80" from "/foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib" has 334 cells (94 skipped: 63 seq; 13 tri-state; 18 no func; 0 dont_use; 0 with 2 outputs; 0 with 3+ outputs). Time = 0.11 sec
ABC: Memory = 19.85 MB. Time = 0.11 sec
ABC: Warning: Detected 9 multi-output cells (for example, "sky130_fd_sc_hd__fa_1").
ABC: + strash
ABC: + &get -n
ABC: + &fraig -x
ABC: + &put
ABC: + scorr
ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
ABC: + dc2
ABC: + dretime
ABC: + strash
ABC: + &get -n
ABC: + &dch -f
ABC: + &nf
ABC: + &put
ABC: + write_blif <abc-temp-dir>/output.blif
ABC:
ABC: YOSYS_ABC_DONE
14.2.2. Re-integrating ABC results.
ABC RESULTS: sky130_fd_sc_hd__a22o_1 cells: 1
ABC RESULTS: sky130_fd_sc_hd__clkinv_1 cells: 1
ABC RESULTS: sky130_fd_sc_hd__nor2_1 cells: 3
ABC RESULTS: sky130_fd_sc_hd__xor2_1 cells: 1
ABC RESULTS: internal signals: 18
ABC RESULTS: input signals: 4
ABC RESULTS: output signals: 4
Removing temp directory.
14.3. Extracting gate netlist of module `\mux' to `<abc-temp-dir>/input.blif'..
14.3.1. Executed ABC.
Extracted 15 gates and 35 wires to a netlist network with 20 inputs and 1 outputs.
Running ABC script: <abc-temp-dir>/abc.script
ABC: UC Berkeley, ABC 1.01 (compiled Feb 14 2026 00:59:35)
ABC: abc 01> empty
ABC: abc 01> source <abc-temp-dir>/abc.script
ABC: + read_blif <abc-temp-dir>/input.blif
ABC: + read_lib -w /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
ABC: Parsing finished successfully. Parsing time = 0.08 sec
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__decap_12" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__decap_3" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__decap_4" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__decap_6" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__decap_8" without logic function.
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfbbn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfbbn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfbbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfsbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfsbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_4".
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__diode_2" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__dlclkp_1" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__dlclkp_2" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__dlclkp_4" without logic function.
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrbn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrbn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrtn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrtn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrtn_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrtp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrtp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrtp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxbn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxbn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtp_1".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_1".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_2".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_4".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_8".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__edfxbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__edfxtp_1".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvn_0".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvn_1".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvn_2".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvn_4".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvn_8".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvp_1".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvp_2".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvp_4".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvp_8".
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__lpflow_bleeder_1" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__lpflow_decapkapwr_12" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__lpflow_decapkapwr_3" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__lpflow_decapkapwr_4" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__lpflow_decapkapwr_6" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__lpflow_decapkapwr_8" without logic function.
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__lpflow_inputisolatch_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfbbn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfbbn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfbbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfrbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfrbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfrtn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfrtp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfrtp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfrtp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfsbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfsbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfstp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfstp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfstp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfxbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfxbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfxtp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfxtp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfxtp_4".
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__sdlclkp_1" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__sdlclkp_2" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__sdlclkp_4" without logic function.
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sedfxbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sedfxbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sedfxtp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sedfxtp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sedfxtp_4".
ABC: Library "sky130_fd_sc_hd__tt_025C_1v80" from "/foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib" has 334 cells (94 skipped: 63 seq; 13 tri-state; 18 no func; 0 dont_use; 0 with 2 outputs; 0 with 3+ outputs). Time = 0.11 sec
ABC: Memory = 19.85 MB. Time = 0.11 sec
ABC: Warning: Detected 9 multi-output cells (for example, "sky130_fd_sc_hd__fa_1").
ABC: + strash
ABC: + &get -n
ABC: + &fraig -x
ABC: + &put
ABC: + scorr
ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
ABC: + dc2
ABC: + dretime
ABC: + strash
ABC: + &get -n
ABC: + &dch -f
ABC: + &nf
ABC: + &put
ABC: + write_blif <abc-temp-dir>/output.blif
ABC:
ABC: YOSYS_ABC_DONE
14.3.2. Re-integrating ABC results.
ABC RESULTS: sky130_fd_sc_hd__mux2i_1 cells: 3
ABC RESULTS: sky130_fd_sc_hd__mux4_2 cells: 4
ABC RESULTS: internal signals: 14
ABC RESULTS: input signals: 20
ABC RESULTS: output signals: 1
Removing temp directory.
14.4. Extracting gate netlist of module `\puf_bit' to `<abc-temp-dir>/input.blif'..
Don't call ABC as there is nothing to map.
14.4.1. Executed ABC.
Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.
Removing temp directory.
14.5. Extracting gate netlist of module `\puf_top' to `<abc-temp-dir>/input.blif'..
Don't call ABC as there is nothing to map.
14.5.1. Executed ABC.
Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.
Removing temp directory.
14.6. Extracting gate netlist of module `\ro' to `<abc-temp-dir>/input.blif'..
Don't call ABC as there is nothing to map.
14.6.1. Executed ABC.
Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.
Removing temp directory.
Removing global temp directory.
Removed 0 unused cells and 114 unused wires.
15. Printing statistics.
=== $paramod\counter\THRESHOLD=16'1111111111111111 ===
+----------Local Count, excluding submodules.
|
45 wires
60 wire bits
5 public wires
20 public wire bits
5 ports
20 port bits
57 cells
2 sky130_fd_sc_hd__a21oi_1
1 sky130_fd_sc_hd__a31o_1
2 sky130_fd_sc_hd__a31oi_1
1 sky130_fd_sc_hd__and2_0
1 sky130_fd_sc_hd__and3_1
2 sky130_fd_sc_hd__and4_1
1 sky130_fd_sc_hd__and4b_1
16 sky130_fd_sc_hd__dfrtp_1
5 sky130_fd_sc_hd__nand2_1
4 sky130_fd_sc_hd__nand3_1
3 sky130_fd_sc_hd__nand4_1
2 sky130_fd_sc_hd__nor2_1
3 sky130_fd_sc_hd__nor2b_1
1 sky130_fd_sc_hd__nor3_1
1 sky130_fd_sc_hd__o2111a_1
1 sky130_fd_sc_hd__o31a_1
9 sky130_fd_sc_hd__xnor2_1
2 sky130_fd_sc_hd__xor2_1
=== arbiter ===
+----------Local Count, excluding submodules.
|
11 wires
12 wire bits
7 public wires
8 public wire bits
6 ports
6 port bits
8 cells
1 sky130_fd_sc_hd__a22o_1
1 sky130_fd_sc_hd__clkinv_1
2 sky130_fd_sc_hd__dfrtp_1
3 sky130_fd_sc_hd__nor2_1
1 sky130_fd_sc_hd__xor2_1
=== mux ===
+----------Local Count, excluding submodules.
|
9 wires
27 wire bits
3 public wires
21 public wire bits
3 ports
21 port bits
7 cells
3 sky130_fd_sc_hd__mux2i_1
4 sky130_fd_sc_hd__mux4_2
=== puf_bit ===
+----------Local Count, excluding submodules.
|
13 wires
81 wire bits
13 public wires
81 public wire bits
6 ports
13 port bits
37 submodules
2 $paramod\counter\THRESHOLD=16'1111111111111111
1 arbiter
2 mux
32 ro
=== puf_top ===
+----------Local Count, excluding submodules.
|
10 wires
52 wire bits
10 public wires
52 public wire bits
8 ports
43 port bits
8 submodules
8 puf_bit
=== ro ===
+----------Local Count, excluding submodules.
|
3 wires
10 wire bits
3 public wires
10 public wire bits
2 ports
2 port bits
7 cells
7 sky130_fd_sc_hd__inv_2
=== design hierarchy ===
+----------Count including submodules.
|
2880 puf_top
57 $paramod\counter\THRESHOLD=16'1111111111111111
8 arbiter
7 mux
7 ro
+----------Count including submodules.
|
1834 wires
4748 wire bits
1066 public wires
3980 public wire bits
744 ports
1363 port bits
- memories
- memory bits
- processes
2880 cells
32 sky130_fd_sc_hd__a21oi_1
8 sky130_fd_sc_hd__a22o_1
16 sky130_fd_sc_hd__a31o_1
32 sky130_fd_sc_hd__a31oi_1
16 sky130_fd_sc_hd__and2_0
16 sky130_fd_sc_hd__and3_1
32 sky130_fd_sc_hd__and4_1
16 sky130_fd_sc_hd__and4b_1
8 sky130_fd_sc_hd__clkinv_1
272 sky130_fd_sc_hd__dfrtp_1
1792 sky130_fd_sc_hd__inv_2
48 sky130_fd_sc_hd__mux2i_1
64 sky130_fd_sc_hd__mux4_2
80 sky130_fd_sc_hd__nand2_1
64 sky130_fd_sc_hd__nand3_1
48 sky130_fd_sc_hd__nand4_1
56 sky130_fd_sc_hd__nor2_1
48 sky130_fd_sc_hd__nor2b_1
16 sky130_fd_sc_hd__nor3_1
16 sky130_fd_sc_hd__o2111a_1
16 sky130_fd_sc_hd__o31a_1
144 sky130_fd_sc_hd__xnor2_1
40 sky130_fd_sc_hd__xor2_1
8 submodules
8 puf_bit
16. Executing Verilog backend.
16.1. Executing BMUXMAP pass.
16.2. Executing DEMUXMAP pass.
Dumping module `$paramod\counter\THRESHOLD=16'1111111111111111'.
Dumping module `\arbiter'.
Dumping module `\mux'.
Dumping module `\puf_bit'.
Dumping module `\puf_top'.
Dumping module `\ro'.
End of script. Logfile hash: 7a3c2d0f43, CPU: user 0.22s system 0.04s, MEM: 64.24 MB peak
Yosys 0.62 (git sha1 7326bb7d6, g++ 13.3.0-6ubuntu2~24.04 -fPIC -O3)
Time spent: 72% 1x abc (0 sec), 6% 1x dfflibmap (0 sec), ...
Run place and route flow¶
Note: add this after line 45 in pnr.tcl to fix [ERROR DRT-0305] Net zero_ of signal type GROUND is not routable by TritonRoute. Move to special nets.
# Promote ground-type nets to special nets
set block [ord::get_db_block]
foreach net [$block getNets] {
if {[$net getSigType] == "GROUND" && ![$net isSpecial]} {
$net setSpecial
}
}
Then run
make pnr-puf
cd puf && TOP=puf_top OUT_DIR=build openroad -exit ../flow/pnr.tcl
OpenROAD 26Q1-990-g15af3a5c0
Features included (+) or not (-): +GPU +GUI +Python
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
============================================
Place & Route: puf_top
Build dir: build
PDK: /foss/pdks
============================================
[INFO ODB-0227] LEF file: /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef, created 14 layers, 25 vias
[WARNING ODB-0220] WARNING (LEFPARS-2008): NOWIREEXTENSIONATPIN statement is obsolete in version 5.6 or later.
The NOWIREEXTENSIONATPIN statement will be ignored. See file /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef at line 2.
[INFO ODB-0227] LEF file: /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef, created 437 library cells
[WARNING ODB-0220] WARNING (LEFPARS-2008): NOWIREEXTENSIONATPIN statement is obsolete in version 5.6 or later.
The NOWIREEXTENSIONATPIN statement will be ignored. See file /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_ef_sc_hd.lef at line 2.
[INFO ODB-0227] LEF file: /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_ef_sc_hd.lef, created 8 library cells
[WARNING STA-0441] set_input_delay relative to a clock defined on the same port/pin not allowed.
Initializing floorplan...
[INFO IFP-0107] Defining die area using utilization: 40.00% and aspect ratio: 1.
[WARNING IFP-0028] Core area lower left (5.000, 5.000) snapped to (5.060, 5.440).
[INFO IFP-0001] Added 82 rows of 487 site unithd.
[INFO IFP-0100] Die BBox: ( 0.000 0.000 ) ( 234.385 234.385 ) um
[INFO IFP-0101] Core BBox: ( 5.060 5.440 ) ( 229.080 228.480 ) um
[INFO IFP-0102] Core area: 49965.421 um^2
[INFO IFP-0103] Total instances area: 20139.315 um^2
[INFO IFP-0104] Effective utilization: 0.403
[INFO IFP-0105] Number of instances: 2880
Placing I/O pins...
Found 0 macro blocks.
Using 2 tracks default min distance between IO pins.
[INFO PPL-0001] Number of available slots 842
[INFO PPL-0002] Number of I/O 43
[INFO PPL-0003] Number of I/O w/sink 18
[INFO PPL-0004] Number of I/O w/o sink 25
[INFO PPL-0005] Slots per section 200
[INFO PPL-0008] Successfully assigned pins to sections.
[INFO PPL-0012] I/O nets HPWL: 2219.62 um.
Building power grid...
[INFO PDN-0001] Inserting grid: core_grid
Running placement...
[INFO GPL-0001] ---- Initialize GPL Main Data Structures
[INFO GPL-0002] DBU: 1000
[INFO GPL-0003] SiteSize: ( 0.460 2.720 ) um
[INFO GPL-0004] CoreBBox: ( 5.060 5.440 ) ( 229.080 228.480 ) um
[INFO GPL-0036] Movable instances area: 34553.139 um^2
[INFO GPL-0037] Total instances area: 34553.139 um^2
[INFO GPL-0035] Pin density area adjust: 1645.603 um^2
[INFO GPL-0032] ---- Initialize Region: Top-level
[INFO GPL-0006] Number of instances: 2880
[INFO GPL-0007] Movable instances: 2880
[INFO GPL-0008] Fixed instances: 0
[INFO GPL-0009] Dummy instances: 0
[INFO GPL-0010] Number of nets: 3155
[INFO GPL-0011] Number of pins: 7955
[INFO GPL-0012] Die BBox: ( 0.000 0.000 ) ( 234.385 234.385 ) um
[INFO GPL-0013] Core BBox: ( 5.060 5.440 ) ( 229.080 228.480 ) um
[INFO GPL-0016] Core area: 49965.421 um^2
[INFO GPL-0014] Region name: top-level.
[INFO GPL-0015] Region area: 49965.421 um^2
[INFO GPL-0017] Fixed instances area: 0.000 um^2
[INFO GPL-0018] Movable instances area: 36198.742 um^2
[INFO GPL-0019] Utilization: 72.448 %
[INFO GPL-0020] Standard cells area: 36198.742 um^2
[INFO GPL-0021] Large instances area: 0.000 um^2
[INFO GPL-0005] ---- Execute Conjugate Gradient Initial Placement.
[INFO GPL-0051] Source of initial instance position counters:
Odb location = 0 Core center = 2880 Region center = 0
[InitialPlace] Iter: 1 conjugate gradient residual: 0.00425508 HPWL: 22360365
[InitialPlace] Iter: 2 conjugate gradient residual: 0.00083139 HPWL: 22150600
[InitialPlace] Iter: 3 conjugate gradient residual: 0.00012633 HPWL: 21082930
[InitialPlace] Iter: 4 conjugate gradient residual: 0.00012633 HPWL: 21086277
[InitialPlace] Iter: 5 conjugate gradient residual: 0.00012633 HPWL: 21085885
[InitialPlace] Iter: 6 conjugate gradient residual: 0.00012633 HPWL: 21090585
[InitialPlace] Iter: 7 conjugate gradient residual: 0.00012633 HPWL: 21087097
[InitialPlace] Iter: 8 conjugate gradient residual: 0.00012633 HPWL: 21092681
[InitialPlace] Iter: 9 conjugate gradient residual: 0.00012633 HPWL: 21089377
[InitialPlace] Iter: 10 conjugate gradient residual: 0.00012633 HPWL: 21093464
[InitialPlace] Iter: 11 conjugate gradient residual: 0.00012633 HPWL: 21090656
[InitialPlace] Iter: 12 conjugate gradient residual: 0.00012633 HPWL: 21094683
[InitialPlace] Iter: 13 conjugate gradient residual: 0.00012633 HPWL: 21090887
[InitialPlace] Iter: 14 conjugate gradient residual: 0.00012633 HPWL: 21095716
[InitialPlace] Iter: 15 conjugate gradient residual: 0.00012633 HPWL: 21091769
[InitialPlace] Iter: 16 conjugate gradient residual: 0.00012633 HPWL: 21095604
[InitialPlace] Iter: 17 conjugate gradient residual: 0.00012633 HPWL: 21092436
[InitialPlace] Iter: 18 conjugate gradient residual: 0.00012633 HPWL: 21096166
[InitialPlace] Iter: 19 conjugate gradient residual: 0.00012633 HPWL: 21092371
[InitialPlace] Iter: 20 conjugate gradient residual: 0.00012633 HPWL: 21096757
[INFO GPL-0033] ---- Initialize Nesterov Region: Top-level
[WARNING GPL-0302] Target density 0.7000 is too low for the available free area.
Automatically adjusting to uniform density 0.7300.
[INFO GPL-0023] Placement target density: 0.7300
[INFO GPL-0024] Movable insts average area: 12.569 um^2
[INFO GPL-0025] Ideal bin area: 17.218 um^2
[INFO GPL-0026] Ideal bin count: 2901
[INFO GPL-0027] Total bin area: 49965.421 um^2
[INFO GPL-0028] Bin count (X, Y): 32 , 32
[INFO GPL-0029] Bin size (W * H): 7.001 * 6.970 um
[INFO GPL-0030] Number of bins: 1024
[INFO GPL-0007] ---- Execute Nesterov Global Placement.
[INFO GPL-0031] HPWL: Half-Perimeter Wirelength
Iteration | Overflow | HPWL (um) | HPWL(%) | Penalty | Group
---------------------------------------------------------------
0 | 0.9920 | 6.261173e+03 | +0.00% | 3.63e-16 |
10 | 0.9900 | 4.350582e+03 | -30.51% | 5.91e-16 |
20 | 0.9899 | 4.136481e+03 | -4.92% | 9.63e-16 |
30 | 0.9900 | 3.982014e+03 | -3.73% | 1.57e-15 |
40 | 0.9902 | 3.925217e+03 | -1.43% | 2.55e-15 |
50 | 0.9903 | 3.882922e+03 | -1.08% | 4.16e-15 |
60 | 0.9904 | 3.866411e+03 | -0.43% | 6.78e-15 |
70 | 0.9904 | 3.860054e+03 | -0.16% | 1.10e-14 |
80 | 0.9903 | 3.850777e+03 | -0.24% | 1.80e-14 |
90 | 0.9903 | 3.848330e+03 | -0.06% | 2.93e-14 |
100 | 0.9902 | 3.848418e+03 | +0.00% | 4.77e-14 |
110 | 0.9900 | 3.847071e+03 | -0.04% | 7.77e-14 |
120 | 0.9900 | 3.858437e+03 | +0.30% | 1.27e-13 |
130 | 0.9895 | 3.921985e+03 | +1.65% | 2.06e-13 |
140 | 0.9880 | 4.105548e+03 | +4.68% | 3.36e-13 |
150 | 0.9845 | 4.492800e+03 | +9.43% | 5.47e-13 |
160 | 0.9780 | 5.080856e+03 | +13.09% | 8.91e-13 |
170 | 0.9671 | 5.945656e+03 | +17.02% | 1.45e-12 |
180 | 0.9556 | 6.907375e+03 | +16.18% | 2.36e-12 |
190 | 0.9325 | 7.905420e+03 | +14.45% | 3.85e-12 |
200 | 0.9059 | 8.909731e+03 | +12.70% | 6.27e-12 |
210 | 0.8786 | 1.000134e+04 | +12.25% | 1.02e-11 |
220 | 0.8438 | 1.130411e+04 | +13.03% | 1.66e-11 |
230 | 0.8019 | 1.224320e+04 | +8.31% | 2.71e-11 |
240 | 0.7606 | 1.343736e+04 | +9.75% | 4.41e-11 |
250 | 0.7325 | 1.419229e+04 | +5.62% | 7.19e-11 |
260 | 0.6965 | 1.485790e+04 | +4.69% | 1.17e-10 |
270 | 0.6539 | 1.519937e+04 | +2.30% | 1.91e-10 |
280 | 0.6043 | 1.547642e+04 | +1.82% | 3.11e-10 |
290 | 0.5859 | 1.559739e+04 | +0.78% | 5.06e-10 |
300 | 0.5403 | 1.569209e+04 | +0.61% | 8.24e-10 |
310 | 0.4999 | 1.572747e+04 | +0.23% | 1.34e-09 |
320 | 0.4630 | 1.611475e+04 | +2.46% | 2.19e-09 |
330 | 0.4261 | 1.562142e+04 | -3.06% | 3.56e-09 |
340 | 0.3788 | 1.581651e+04 | +1.25% | 5.80e-09 |
350 | 0.3478 | 1.566638e+04 | -0.95% | 9.45e-09 |
360 | 0.3152 | 1.577200e+04 | +0.67% | 1.41e-08 |
370 | 0.2973 | 1.565692e+04 | -0.73% | 2.07e-08 |
380 | 0.2681 | 1.574519e+04 | +0.56% | 3.05e-08 |
390 | 0.2420 | 1.570717e+04 | -0.24% | 4.49e-08 |
400 | 0.2160 | 1.582443e+04 | +0.75% | 6.62e-08 |
410 | 0.1919 | 1.587806e+04 | +0.34% | 9.75e-08 |
420 | 0.1683 | 1.611351e+04 | +1.48% | 1.44e-07 |
430 | 0.1459 | 1.631046e+04 | +1.22% | 2.12e-07 |
440 | 0.1268 | 1.643247e+04 | +0.75% | 3.12e-07 |
450 | 0.1075 | 1.659848e+04 | +1.01% | 4.59e-07 |
454 | 0.0986 | 1.667845e+04 | | 5.58e-07 |
---------------------------------------------------------------
[INFO GPL-1001] Global placement finished at iteration 454
[INFO GPL-1002] Placed Cell Area 36198.7417
[INFO GPL-1003] Available Free Area 49965.4208
[INFO GPL-1004] Minimum Feasible Density 0.7300 (cell_area / free_area)
[INFO GPL-1006] Suggested Target Densities:
[INFO GPL-1007] - For 90% usage of free space: 0.8050
[INFO GPL-1008] - For 80% usage of free space: 0.9056
[INFO GPL-1014] Final placement area: 36198.74 (+0.00%)
Placement Analysis
---------------------------------
total displacement 5790.4 u
average displacement 2.0 u
max displacement 6.8 u
original HPWL 16730.0 u
legalized HPWL 22106.8 u
delta HPWL 32 %
Running clock tree synthesis...
[WARNING EST-0027] no estimated parasitics. Using wire load models.
Iteration | Area | Resized | Buffers | Nets repaired | Remaining
---------------------------------------------------------------------
0 | +0.0% | 0 | 0 | 0 | 2899
final | +0.0% | 0 | 0 | 0 | 0
---------------------------------------------------------------------
[INFO CTS-0050] Root buffer is sky130_fd_sc_hd__clkbuf_16.
[INFO CTS-0051] Sink buffer is sky130_fd_sc_hd__clkbuf_4.
[INFO CTS-0052] The following clock buffers will be used for CTS:
sky130_fd_sc_hd__clkbuf_4
sky130_fd_sc_hd__clkbuf_8
sky130_fd_sc_hd__clkbuf_16
[INFO CTS-0049] Characterization buffer is sky130_fd_sc_hd__clkbuf_16.
[INFO CTS-0007] Net "clk" found for clock "clk".
[INFO CTS-0010] Clock net "clk" has 272 sinks.
[INFO CTS-0008] TritonCTS found 1 clock nets.
[INFO CTS-0097] Characterization used 3 buffer(s) types.
[INFO CTS-0201] 0 blockages from hard placement blockages and placed macros will be used.
[INFO CTS-0027] Generating H-Tree topology for net clk.
[INFO CTS-0028] Total number of sinks: 272.
[INFO CTS-0090] Sinks will be clustered based on buffer max cap.
[INFO CTS-0030] Number of static layers: 0.
[INFO CTS-0020] Wire segment unit: 13600 dbu (13 um).
[INFO CTS-0206] Best clustering solution was found from clustering size of 30 and clustering diameter of 50.
[INFO CTS-0019] Total number of sinks after clustering: 45.
[INFO CTS-0024] Normalized sink region: [(1.00037, 4.35651), (15.7233, 16.0667)].
[INFO CTS-0025] Width: 14.7229.
[INFO CTS-0026] Height: 11.7102.
Level 1
Direction: Horizontal
Sinks per sub-region: 23
Sub-region size: 7.3614 X 11.7102
[INFO CTS-0034] Segment length (rounded): 4.
Level 2
Direction: Vertical
Sinks per sub-region: 12
Sub-region size: 7.3614 X 5.8551
[INFO CTS-0034] Segment length (rounded): 2.
[INFO CTS-0032] Stop criterion found. Max number of sinks is 15.
[INFO CTS-0035] Number of sinks covered: 45.
[INFO CTS-0018] Created 50 clock buffers.
[INFO CTS-0012] Minimum number of buffers in the clock path: 3.
[INFO CTS-0013] Maximum number of buffers in the clock path: 3.
[INFO CTS-0015] Created 50 clock nets.
[INFO CTS-0016] Fanout distribution for the current clock = 2:1, 3:1, 4:1, 5:5, 6:21, 7:16, 9:2, 13:1, 14:1..
[INFO CTS-0017] Max level of the clock tree: 2.
[INFO CTS-0098] Clock net "clk"
[INFO CTS-0099] Sinks 304
[INFO CTS-0100] Leaf buffers 45
[INFO CTS-0101] Average sink wire length 281.88 um
[INFO CTS-0102] Path depth 2 - 3
[INFO CTS-0207] Dummy loads inserted 32
Placement Analysis
---------------------------------
total displacement 309.5 u
average displacement 0.1 u
max displacement 6.6 u
original HPWL 24320.3 u
legalized HPWL 24450.9 u
delta HPWL 1 %
Running routing...
[INFO DRT-0149] Reading tech and libs.
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer mcon
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer mcon
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via2
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via2
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via3
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via3
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via4
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via4
Units: 1000
Number of layers: 13
Number of macros: 445
Number of vias: 29
Number of viarulegen: 25
[INFO DRT-0150] Reading design.
[WARNING DRT-0120] Large net rst_n has 273 pins which may impact routing performance. Consider optimization.
Design: puf_top
Die area: ( 0 0 ) ( 234385 234385 )
Number of track patterns: 12
Number of DEF vias: 0
Number of components: 2962
Number of terminals: 45
Number of snets: 3
Number of nets: 3205
[INFO DRT-0167] List of default vias:
Layer via
default via: M1M2_PR
Layer via2
default via: M2M3_PR
Layer via3
default via: M3M4_PR
Layer via4
default via: M4M5_PR
[INFO DRT-0162] Library cell analysis.
[INFO DRT-0163] Instance analysis.
[INFO DRT-0164] Number of unique instances = 56.
[INFO DRT-0168] Init region query.
[INFO DRT-0024] Complete FR_MASTERSLICE.
[INFO DRT-0024] Complete licon.
[INFO DRT-0024] Complete li1.
[INFO DRT-0024] Complete mcon.
[INFO DRT-0024] Complete met1.
[INFO DRT-0024] Complete via.
[INFO DRT-0024] Complete met2.
[INFO DRT-0024] Complete via2.
[INFO DRT-0024] Complete met3.
[INFO DRT-0024] Complete via3.
[INFO DRT-0024] Complete met4.
[INFO DRT-0024] Complete via4.
[INFO DRT-0024] Complete met5.
[INFO DRT-0033] FR_MASTERSLICE shape region query size = 0.
[INFO DRT-0033] licon shape region query size = 0.
[INFO DRT-0033] li1 shape region query size = 64203.
[INFO DRT-0033] mcon shape region query size = 0.
[INFO DRT-0033] met1 shape region query size = 11213.
[INFO DRT-0033] via shape region query size = 1870.
[INFO DRT-0033] met2 shape region query size = 1147.
[INFO DRT-0033] via2 shape region query size = 1496.
[INFO DRT-0033] met3 shape region query size = 1140.
[INFO DRT-0033] via3 shape region query size = 1496.
[INFO DRT-0033] met4 shape region query size = 433.
[INFO DRT-0033] via4 shape region query size = 41.
[INFO DRT-0033] met5 shape region query size = 59.
[INFO DRT-0165] Start pin access.
[INFO DRT-0078] Complete 432 pins.
[INFO DRT-0081] Complete 56 unique inst patterns.
[INFO DRT-0084] Complete 1474 groups.
#scanned instances = 2962
#unique instances = 56
#stdCellGenAp = 1613
#stdCellValidPlanarAp = 36
#stdCellValidViaAp = 1263
#stdCellPinNoAp = 0
#stdCellPinCnt = 8060
#instTermValidViaApCnt = 0
#macroGenAp = 0
#macroValidPlanarAp = 0
#macroValidViaAp = 0
#macroNoAp = 0
[INFO DRT-0166] Complete pin access.
[INFO DRT-0267] cpu time = 00:00:38, elapsed time = 00:00:38, memory = 237.24 (MB), peak = 237.01 (MB)
[INFO DRT-0157] Number of guides: 13370
[INFO DRT-0169] Post process guides.
[INFO DRT-0176] GCELLGRID X 0 DO 33 STEP 6900 ;
[INFO DRT-0177] GCELLGRID Y 0 DO 33 STEP 6900 ;
[INFO DRT-0028] Complete FR_MASTERSLICE.
[INFO DRT-0028] Complete licon.
[INFO DRT-0028] Complete li1.
[INFO DRT-0028] Complete mcon.
[INFO DRT-0028] Complete met1.
[INFO DRT-0028] Complete via.
[INFO DRT-0028] Complete met2.
[INFO DRT-0028] Complete via2.
[INFO DRT-0028] Complete met3.
[INFO DRT-0028] Complete via3.
[INFO DRT-0028] Complete met4.
[INFO DRT-0028] Complete via4.
[INFO DRT-0028] Complete met5.
[INFO DRT-0178] Init guide query.
[INFO DRT-0035] Complete FR_MASTERSLICE (guide).
[INFO DRT-0035] Complete licon (guide).
[INFO DRT-0035] Complete li1 (guide).
[INFO DRT-0035] Complete mcon (guide).
[INFO DRT-0035] Complete met1 (guide).
[INFO DRT-0035] Complete via (guide).
[INFO DRT-0035] Complete met2 (guide).
[INFO DRT-0035] Complete via2 (guide).
[INFO DRT-0035] Complete met3 (guide).
[INFO DRT-0035] Complete via3 (guide).
[INFO DRT-0035] Complete met4 (guide).
[INFO DRT-0035] Complete via4 (guide).
[INFO DRT-0035] Complete met5 (guide).
[INFO DRT-0036] FR_MASTERSLICE guide region query size = 0.
[INFO DRT-0036] licon guide region query size = 0.
[INFO DRT-0036] li1 guide region query size = 5358.
[INFO DRT-0036] mcon guide region query size = 0.
[INFO DRT-0036] met1 guide region query size = 3556.
[INFO DRT-0036] via guide region query size = 0.
[INFO DRT-0036] met2 guide region query size = 1478.
[INFO DRT-0036] via2 guide region query size = 0.
[INFO DRT-0036] met3 guide region query size = 23.
[INFO DRT-0036] via3 guide region query size = 0.
[INFO DRT-0036] met4 guide region query size = 0.
[INFO DRT-0036] via4 guide region query size = 0.
[INFO DRT-0036] met5 guide region query size = 0.
[INFO DRT-0179] Init gr pin query.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 241.27 (MB), peak = 241.01 (MB)
[INFO DRT-0245] skipped writing guide updates to database.
[INFO DRT-0185] Post process initialize RPin region query.
[INFO DRT-0181] Start track assignment.
[INFO DRT-0184] Done with 6836 vertical wires in 1 frboxes and 3579 horizontal wires in 1 frboxes.
[INFO DRT-0186] Done with 343 vertical wires in 1 frboxes and 813 horizontal wires in 1 frboxes.
[INFO DRT-0182] Complete track assignment.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 256.04 (MB), peak = 255.76 (MB)
[INFO DRT-0187] Start routing data preparation.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 256.04 (MB), peak = 255.76 (MB)
[INFO DRT-0194] Start detail routing.
[INFO DRT-0195] Start 0th optimization iteration.
Completing 10% with 0 violations.
elapsed time = 00:00:01, memory = 271.45 (MB).
Completing 20% with 0 violations.
elapsed time = 00:00:02, memory = 283.68 (MB).
Completing 30% with 0 violations.
elapsed time = 00:00:03, memory = 310.52 (MB).
Completing 40% with 77 violations.
elapsed time = 00:00:04, memory = 310.52 (MB).
Completing 50% with 77 violations.
elapsed time = 00:00:06, memory = 322.92 (MB).
Completing 60% with 77 violations.
elapsed time = 00:00:07, memory = 322.92 (MB).
Completing 70% with 124 violations.
elapsed time = 00:00:09, memory = 322.92 (MB).
Completing 80% with 124 violations.
elapsed time = 00:00:10, memory = 322.92 (MB).
Completing 90% with 183 violations.
elapsed time = 00:00:13, memory = 322.92 (MB).
Completing 100% with 253 violations.
elapsed time = 00:00:14, memory = 327.49 (MB).
[INFO DRT-0199] Number of violations = 395.
Viol/Layer li1 mcon met1 via met2
Cut Spacing 0 2 0 0 0
Metal Spacing 0 0 92 0 25
Min Hole 0 0 3 0 0
Recheck 3 0 108 0 31
Short 0 0 126 2 3
[INFO DRT-0267] cpu time = 00:00:14, elapsed time = 00:00:14, memory = 617.33 (MB), peak = 616.89 (MB)
Total wire length = 29801 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 15714 um.
Total wire length on LAYER met2 = 13400 um.
Total wire length on LAYER met3 = 686 um.
Total wire length on LAYER met4 = 0 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 13492.
Up-via summary (total 13492):
------------------------
FR_MASTERSLICE 0
li1 7539
met1 5931
met2 22
met3 0
met4 0
------------------------
13492
[INFO DRT-0195] Start 1st optimization iteration.
Completing 10% with 395 violations.
elapsed time = 00:00:00, memory = 617.34 (MB).
Completing 20% with 395 violations.
elapsed time = 00:00:02, memory = 617.34 (MB).
Completing 30% with 395 violations.
elapsed time = 00:00:03, memory = 617.34 (MB).
Completing 40% with 292 violations.
elapsed time = 00:00:04, memory = 617.34 (MB).
Completing 50% with 292 violations.
elapsed time = 00:00:06, memory = 617.34 (MB).
Completing 60% with 292 violations.
elapsed time = 00:00:07, memory = 617.34 (MB).
Completing 70% with 226 violations.
elapsed time = 00:00:09, memory = 617.34 (MB).
Completing 80% with 226 violations.
elapsed time = 00:00:10, memory = 617.34 (MB).
Completing 90% with 136 violations.
elapsed time = 00:00:12, memory = 617.34 (MB).
Completing 100% with 74 violations.
elapsed time = 00:00:13, memory = 617.34 (MB).
[INFO DRT-0199] Number of violations = 74.
Viol/Layer met1 met2
Metal Spacing 21 3
Short 50 0
[INFO DRT-0267] cpu time = 00:00:13, elapsed time = 00:00:13, memory = 617.61 (MB), peak = 617.27 (MB)
Total wire length = 29573 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 15600 um.
Total wire length on LAYER met2 = 13272 um.
Total wire length on LAYER met3 = 701 um.
Total wire length on LAYER met4 = 0 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 13493.
Up-via summary (total 13493):
------------------------
FR_MASTERSLICE 0
li1 7550
met1 5917
met2 26
met3 0
met4 0
------------------------
13493
[INFO DRT-0195] Start 2nd optimization iteration.
Completing 10% with 74 violations.
elapsed time = 00:00:00, memory = 617.61 (MB).
Completing 20% with 74 violations.
elapsed time = 00:00:00, memory = 617.61 (MB).
Completing 30% with 76 violations.
elapsed time = 00:00:00, memory = 617.61 (MB).
Completing 40% with 76 violations.
elapsed time = 00:00:01, memory = 617.61 (MB).
Completing 50% with 76 violations.
elapsed time = 00:00:03, memory = 617.61 (MB).
Completing 60% with 65 violations.
elapsed time = 00:00:05, memory = 617.61 (MB).
Completing 70% with 65 violations.
elapsed time = 00:00:06, memory = 617.61 (MB).
Completing 80% with 26 violations.
elapsed time = 00:00:07, memory = 617.61 (MB).
Completing 90% with 26 violations.
elapsed time = 00:00:07, memory = 617.61 (MB).
Completing 100% with 26 violations.
elapsed time = 00:00:07, memory = 617.61 (MB).
[INFO DRT-0199] Number of violations = 26.
Viol/Layer met1
Metal Spacing 11
Short 15
[INFO DRT-0267] cpu time = 00:00:07, elapsed time = 00:00:07, memory = 617.61 (MB), peak = 617.27 (MB)
Total wire length = 29573 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 15623 um.
Total wire length on LAYER met2 = 13263 um.
Total wire length on LAYER met3 = 687 um.
Total wire length on LAYER met4 = 0 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 13482.
Up-via summary (total 13482):
------------------------
FR_MASTERSLICE 0
li1 7542
met1 5918
met2 22
met3 0
met4 0
------------------------
13482
[INFO DRT-0195] Start 3rd guides tiles iteration.
Completing 10% with 26 violations.
elapsed time = 00:00:00, memory = 617.61 (MB).
Completing 20% with 26 violations.
elapsed time = 00:00:00, memory = 617.61 (MB).
Completing 30% with 26 violations.
elapsed time = 00:00:00, memory = 617.61 (MB).
Completing 40% with 26 violations.
elapsed time = 00:00:00, memory = 617.61 (MB).
Completing 50% with 26 violations.
elapsed time = 00:00:00, memory = 617.61 (MB).
Completing 60% with 1 violations.
elapsed time = 00:00:00, memory = 617.61 (MB).
Completing 70% with 1 violations.
elapsed time = 00:00:00, memory = 617.61 (MB).
Completing 80% with 1 violations.
elapsed time = 00:00:00, memory = 617.61 (MB).
Completing 90% with 1 violations.
elapsed time = 00:00:00, memory = 617.61 (MB).
Completing 100% with 0 violations.
elapsed time = 00:00:00, memory = 617.61 (MB).
[INFO DRT-0199] Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 617.61 (MB), peak = 617.27 (MB)
Total wire length = 29598 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 15603 um.
Total wire length on LAYER met2 = 13278 um.
Total wire length on LAYER met3 = 716 um.
Total wire length on LAYER met4 = 0 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 13513.
Up-via summary (total 13513):
------------------------
FR_MASTERSLICE 0
li1 7541
met1 5937
met2 35
met3 0
met4 0
------------------------
13513
[INFO DRT-0198] Complete detail routing.
Total wire length = 29598 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 15603 um.
Total wire length on LAYER met2 = 13278 um.
Total wire length on LAYER met3 = 716 um.
Total wire length on LAYER met4 = 0 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 13513.
Up-via summary (total 13513):
------------------------
FR_MASTERSLICE 0
li1 7541
met1 5937
met2 35
met3 0
met4 0
------------------------
13513
[INFO DRT-0267] cpu time = 00:00:36, elapsed time = 00:00:36, memory = 617.66 (MB), peak = 617.27 (MB)
[INFO DRT-0180] Post processing.
Adding filler cells...
[INFO DPL-0001] Placed 5469 filler instances.
Running final analysis...
[WARNING EST-0018] wire capacitance for corner default is zero. Use the set_wire_rc command to set wire resistance and capacitance.
Design area 20896 um^2 42% utilization.
Writing outputs...
============================================
Place & Route complete!
DEF: build/puf_top.def
Netlist: build/puf_top_pnr.v
Reports: build/puf_top_*.rpt
============================================
Check timing reports - any violations? Fix if needed¶
Startpoint: genblk1[4].myBuffer/race_arb/_10_
(rising edge-triggered flip-flop clocked by clk)
Endpoint: uo_out[4] (output port clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.45 0.45 clock network delay (propagated)
0.00 0.45 ^ genblk1[4].myBuffer/race_arb/_10_/CLK (sky130_fd_sc_hd__dfrtp_1)
0.37 0.82 ^ genblk1[4].myBuffer/race_arb/_10_/Q (sky130_fd_sc_hd__dfrtp_1)
0.08 0.90 v genblk1[4].myBuffer/race_arb/_04_/Y (sky130_fd_sc_hd__clkinv_1)
0.06 0.96 ^ genblk1[4].myBuffer/race_arb/_05_/Y (sky130_fd_sc_hd__nor2_1)
0.00 0.96 ^ uo_out[4] (out)
0.96 data arrival time
20.00 20.00 clock clk (rise edge)
0.00 20.00 clock network delay (propagated)
-0.50 19.50 clock uncertainty
0.00 19.50 clock reconvergence pessimism
-5.00 14.50 output external delay
14.50 data required time
---------------------------------------------------------
14.50 data required time
-0.96 data arrival time
---------------------------------------------------------
13.54 slack (MET)
Generate GDS, view layout - find your flip-flops, trace the clock¶
make gds-puf
cd puf && klayout -zz -r ../flow/def2gds.rb \
-rd def_file=build/puf_top.def -rd gds_file=build/puf_top.gds
============================================
DEF to GDS Conversion
============================================
Loading standard cell GDS...
Reading DEF: build/puf_top.def
Writing GDS: build/puf_top.gds
============================================
GDS written successfully!
File size: 6578260 bytes
============================================
View layout¶
make view-puf
TODOs¶
** Implement a scrambler to improve the PUF.. * Should I do something to change the constraints file to specify which cell is the driving cell and to add an output load .. ? * Try Openroad UI