Session 2:CMOS Logic Implementation – OR Gate¶
Logic Concept¶
Before implementing digital systems at a higher level, I explored how logic gates are built at the transistor level.
The OR gate follows the logic:
This means the output is HIGH when at least one input is HIGH.
CMOS Implementation¶
To understand this physically, I analyzed how an OR gate can be built using CMOS technology.
The circuit is composed of: - PMOS transistors (pull-up network) - NMOS transistors (pull-down network)
The correct arrangement ensures proper logical behavior.
SPICE Description¶
A CMOS implementation can be described using transistor-level modeling:
* 1 V power supply
vsup VDD 0 1
* Pull-up network (PMOS)
Mp1 npu A VDD VDD mosp L=0.35u W=2u
Mp2 nOUT B npu VDD mosp L=0.35u W=2u
* Pull-down network (NMOS)
Mn1 nOUT A 0 0 mosn L=0.35u W=2u
Mn2 nOUT B 0 0 mosn L=0.35u W=2u
* Inverter (output stage)
Mp3 AND nOUT VDD VDD mosp L=0.35u W=2u
Mn3 AND nOUT 0 0 mosn L=0.35u W=2u
This describes how the logic is physically implemented at the transistor level.
Breadboard Implementation
I implemented the OR gate using discrete MOSFETs on a breadboard.
The circuit includes:
PMOS transistors for pull-up NMOS transistors for pull-down input switches (A and B) LED as output indicator
Testing All Input States
I tested all possible input combinations:
Case 1: A = 0, B = 0
Output is LOW, as expected.
Case 2: A = 0, B = 1
Output is HIGH.
Case 3: A = 1, B = 0
Output is HIGH.
Case 4: A = 1, B = 1
Output remains HIGH.
Key Insight
This experiment helped me understand that:
digital logic is physically built using transistors CMOS combines PMOS and NMOS for efficient switching logic gates are not abstract — they are real circuits the same logic seen in Verilog is implemented at hardware level
This bridges the gap between theoretical logic design and physical electronics.
Circuit Simulation with NGSpice¶
Running the Simulation¶
To analyze the behavior of logic gates at the circuit level, I used NGSpice, a circuit simulation tool.
ngspice and.sp
The simulation initializes the circuit and performs a transient analysis.
Simulation Output
The terminal shows important information such as:
node voltages current values model parameters (NMOS/PMOS)
This confirms that the circuit is being evaluated at the electrical level.
Input Signals
I analyzed the input signals over time using transient plots.
The signals represent the logical inputs (A and B) changing over time.
Output Signal
Finally, I plotted the output of the AND gate:
plot v(AND)
Key Insight
Using NGSpice allowed me to:
simulate circuits at the transistor level observe voltage behavior over time validate logic gates using real electrical models connect digital logic with analog circuit behavior
This reinforces the idea that digital systems are built on top of analog electrical principles.
Conclusion¶
In this session, I explored how digital logic is implemented at the transistor level using CMOS technology and how it can be analyzed through circuit simulation.
I designed and tested an OR gate using: - CMOS transistor networks (PMOS and NMOS) - SPICE modeling for circuit-level description - NGSpice for simulation and waveform analysis - A physical breadboard implementation using discrete components
Through this process, I verified all possible input combinations and confirmed that the circuit behaves according to the expected truth table.
One of the most important insights from this session is that digital systems are fundamentally analog. Logical operations such as OR and AND are not abstract concepts, but are physically implemented using transistors that control voltage and current.
Additionally, using NGSpice allowed me to observe real electrical behavior over time, reinforcing the relationship between circuit design and signal behavior.
This session helped me bridge the gap between:
- Boolean logic
- Hardware description
- Transistor-level implementation
- Real-world circuit behavior
Overall, this provides a strong foundation for understanding how complex digital systems are built from basic electronic components.