Session 3: Schematic & Simulation

Overview

In this session, I focused on simulating a NAND gate at the transistor level using NGSpice.

The objective was to: - understand CMOS behavior in simulation - analyze transient responses - compare ideal transistor models vs real PDK models

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CMOS NAND Logic

A NAND gate outputs LOW only when both inputs are HIGH.

This behavior is implemented using: - PMOS transistors in parallel (pull-up network) - NMOS transistors in series (pull-down network)

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NGSpice Simulation (Basic Model)

I first simulated the NAND gate using basic NMOS and PMOS models.

* NAND gate ngspice


.model mosn NMOS Level=49 version=3.3.0 tox=10n
.model mosp PMOS level=49 version=3.3.0 tox=10n

vsup VDD 0 1

Mp1 nOUT A VDD VDD mosp L=0.35u W=2u
Mp2 nOUT B VDD VDD mosp L=0.35u W=2u

Mn1 nOUT A npd 0 mosn L=0.35u W=2u
Mn2 npd B 0 0 mosn L=0.35u W=2u

vin1 A 0 PWL(0 0 2mS 0 2.001mS 1V 3mS 1V 3.001mS 0)
vin2 B 0 PWL(0 0 1mS 0 1.001mS 1V 2.5mS 1V 2.5001mS 0)

.control
tran 100n 4m
plot v(A)
plot v(B)
plot v(nOUT)
.endc

Simulation Results

The results show:

input signals (A and B) output signal (nOUT)

The output behaves as expected for a NAND gate:

HIGH for most cases LOW only when both inputs are HIGH

NGSpice with PDK (Sky130)

To increase realism, I used the Sky130 PDK models

.lib /foss/pdks/sky130A/libs.tech/ngspice/sky130.lib.spice tt

vsup VDD 0 1

Mp1 nOUT A VDD VDD sky130_fd_pr__pfet_01v8 L=0.35u W=2u
Mp2 nOUT B VDD VDD sky130_fd_pr__pfet_01v8 L=0.35u W=2u

Mn1 nOUT A npd 0 sky130_fd_pr__nfet_01v8 L=0.35u W=2u
Mn2 npd B 0 0 sky130_fd_pr__nfet_01v8 L=0.35u W=2u

.control
tran 100n 4m
plot v(A)
plot v(B)
plot v(nOUT)
.endc

PDK Simulation Results

Using real transistor models introduces:

more realistic transitions non-ideal behavior closer approximation to real silicon Key Insight

This session demonstrated that:

CMOS logic can be accurately simulated at transistor level SPICE allows detailed electrical analysis PDK models provide realistic behavior of fabricated devices digital logic depends on analog electrical characteristics

Conclusion

In this session, I simulated a NAND gate using both ideal and real transistor models.

This allowed me to understand the difference between theoretical behavior and real-world circuit performance.

Using NGSpice and PDK libraries, I observed how transistor-level effects influence digital logic, which is essential for designing reliable integrated circuits.