Session 04 — Minerva: 8-bit Educational Computer¶

Objective¶

The objective of this session was to understand the relationship between high-level digital system design and its physical implementation. This includes defining a complete computer architecture, exploring standard cells in a real fabrication process (Sky130), and connecting abstract CPU components to their transistor-level realization.

Summary¶

Layout → Verification (DRC/LVS) → Tape Out → Fabrication → Delivery

This workflow represents the transformation from a logical design into a physical integrated circuit.

Assignment 1 — Block Diagram¶

Project Overview¶

The system designed in this project is Minerva, an educational 8-bit computer named after the Roman goddess of wisdom. The purpose of Minerva is to demonstrate the principles of computer architecture, sequential execution, and digital logic through a simple but meaningful task:

Generating perfect squares using the sum of consecutive odd numbers and transmitting the results via UART.

Mathematically:

A = 0
B = 1
Repeat: A = A + B
B = B + 2

This produces: 1, 4, 9, 16, 25…

System Architecture¶

Minerva is composed of the following modules:

Program Counter (PC)
ROM (Program Memory)
Instruction Register (IR)
Control Unit
8-bit ALU
Register A (Accumulator)
Register B (Odd Increment)
Register N (Loop Counter)
Flags (Zero, Carry)
Branch / Jump Logic
UART TX
Top module (integration)

Block Diagram (Conceptual)¶

Data Flow Explanation¶

The Program Counter (PC) fetches instructions from ROM.
The instruction is stored in the Instruction Register (IR).
The Control Unit decodes the instruction and generates control signals.
The ALU performs arithmetic operations (addition and subtraction).
Registers A, B, and N store intermediate values:
A: accumulated result (square)
B: current odd number
N: number of iterations remaining
Flags (Zero, Carry) are updated after operations.
Branch logic determines whether to loop or stop.
Results are transmitted through UART TX.

Assignment 2 — Exploring a Standard Cell¶

The Sky130 standard cell library was explored using KLayout.

Inverter: sky130_fd_sc_hd__inv_1¶

An inverter is one of the most fundamental digital logic cells. It implements the NOT operation.

At the physical level, the inverter consists of:

One PMOS transistor (pull-up network)
One NMOS transistor (pull-down network)

Layers Identified¶

The following layers were observed:

Poly (Polysilicon): forms the transistor gates
Diffusion (Active): regions where current flows
Metal layers (Metal1, Metal2): routing connections
Contacts/Vias: connections between layers

Interpretation¶

This shows that even the simplest logic operation is built from physical transistor structures. All digital circuits, including the CPU designed in this project, are ultimately composed of these basic elements.

Assignment 3 — Connect the Dots¶

To connect the high-level architecture of Minerva with its physical implementation, we analyze how each block would be constructed using standard cells.

Example: Registers and Flip-Flops¶

Registers such as A, B, and N are implemented using:

D Flip-Flops (sky130_fd_sc_hd__dfxtp_1)

Each 8-bit register requires 8 flip-flops.

Estimated Flip-Flop Usage¶

Register A → 8 FF
Register B → 8 FF
Register N → 8 FF
Instruction Register → 8 FF
Program Counter (4-bit) → 4 FF

Total ≈ 36 flip-flops

Combinational Logic¶

Other blocks are implemented using combinational standard cells:

ALU → adders, multiplexers, logic gates
Control Unit → combinational decoding logic
Branch logic → comparators and gates

Key Insight¶

The Minerva computer, while conceptually simple, would be physically implemented as a network of:

Hundreds of transistors
Dozens of flip-flops
Standard cells interconnected through metal layers

This demonstrates the bridge between abstract CPU design and real silicon implementation.

Reflection¶

This session made it clear that digital systems are not just abstract diagrams but physical structures built from transistors. Designing Minerva helped reinforce how:

High-level architecture maps to real hardware
Registers rely on flip-flops
Control logic becomes combinational gates
Entire CPUs are built from standard cells

Understanding this connection is essential for moving from simulation to real chip fabrication.