Class 4 – Cache Timing and Flush+Reload Attack¶

Part 1: Timing the Cache vs Main Memory¶

Objective¶

To measure the difference between accessing data from the CPU cache and main memory (DRAM) and understand how timing differences can be used in cache side-channel attacks.

Methodology¶

Two memory access times were measured:

1. Cache (L1) Access¶

The memory address was accessed first to load the data into the CPU cache.
The access time was measured using:

measure_one_block_access_time()

Since the data was already cached, the access time was expected to be lower.

2. DRAM Access¶

The cache line was removed using:

clflush()

The access time was measured again.
Since the data was no longer in the cache, the processor retrieved it from main memory, resulting in higher latency.

Experimental Results¶

The program was executed using:

make run

The measured results were:

             Cache(L1)  DRAM
Minimum            86    451
Bottom decile      91    459
Median             98    465
Top decile        101   1292
Maximum           101   1292

Screenshot: Cache and DRAM timing results

Observation¶

The median access times were:

Memory Type	Latency
Cache (L1)	98 cycles
DRAM	465 cycles

The difference was:

465 - 98 = 367 cycles

Therefore, accessing data from DRAM required approximately 367 more CPU cycles compared to accessing data from the cache.

This demonstrates that cached data can be accessed much faster than data stored in main memory.

Selecting a Threshold Value¶

To distinguish between cache hits and DRAM accesses, a threshold value was selected.

Observed values:

Maximum cache latency:

101 cycles

Minimum DRAM latency:

451 cycles

Since there was a clear separation, the selected threshold was:

250 cycles

Decision rule:

Access time < 250 cycles  → Cache Hit
Access time > 250 cycles  → DRAM Access

This threshold was used for the Flush+Reload attack in Part 2.

Part 2: Flush+Reload Cache Side Channel Attack¶

Objective¶

To recover a secret value from a victim program by exploiting differences between cache access time and DRAM access time using the Flush+Reload side-channel attack.

Attack Method¶

The Flush+Reload attack works in three steps:

1. Flush¶

The attacker removes data from the CPU cache using:

clflush()

This ensures that the data is not currently cached.

2. Wait¶

The attacker waits briefly while the victim program executes.

If the victim accesses the secret-dependent memory location, that data is loaded into the cache.

3. Reload¶

The attacker measures the access time again.

Results:

Fast access  → Cache hit → Victim accessed the data
Slow access  → DRAM access → Victim did not access the data

The threshold used:

250 cycles

Result¶

The victim program generated the secret:

Flag: 568

The attacker successfully recovered:

Flag: 568

This confirms that the Flush+Reload cache side-channel attack was successful.

Screenshot¶

Discussion: Preventing Cache Side-Channel Attacks¶

How can the victim prevent this cache leak?¶

The victim should avoid memory access patterns that depend on secret values.

Example of vulnerable code:

value = buffer[secret];

The memory location changes depending on the secret value, which can reveal information through cache timing.

Possible protections include:

Using constant-time algorithms.
Avoiding secret-dependent memory access.
Preventing memory sharing with untrusted processes.
Using hardware and software security mechanisms designed to reduce cache leakage.

Learning Outcome¶

This experiment demonstrated that differences in cache and DRAM access times can reveal information about a program’s behavior.

The Flush+Reload attack shows how attackers can exploit hardware performance features as a side channel to recover sensitive information.