Class 4 Microarchitecture security

Setting Up Environment

sudo apt install make gcc

Part 1: Timing the Cache vs. Main Memory

Cache (L1) Median Latency: 40 cycles

DRAM Median Latency: 318 cycles

How big is the difference?

Difference in cycles: 318-40=278” cycles

Performance factor: 318/40≈8” times

The typical Cache (L1) latency measured was 40 cycles (median), while the typical DRAM latency was 318 cycles (median).

The DRAM access is significantly slower, taking nearly 8 times longer (a difference of 278 clock cycles) compared to an L1 cache hit.

Discussion Question 1-2: Choosing a Threshold

Maximum Cache latency was 43 cycles.

Minimum DRAM latency was 243 cycles.

There is a huge, clear gap between 43 and 243.

Part 2: Capture the Flag with Flush+Reload

In this section, I tried getting into our zoom video and homework guides for several times. To get even into this present work environment, I spent more than 12 hours figuring out every bits of the tasks.

I found it very challenging besides not being able to get the victim-attacker results as required. Getting AI assisted helps, I could not fix it to get the same value of victim and attacker without having the basic concepts of this course. However, it is helping me to learn some concepts that would atleast raise by learning cpacity.